PHD3N20L Datasheet, PDF (1/7 Pages) NXP Semiconductors – PowerMOS transistor Logic level FET

Philips Semiconductors
PowerMOS transistor
Logic level FET
Product specification
PHD3N20L
GENERAL DESCRIPTION
N-channel enhancement mode logic
level field-effect power transistor in a
plastic envelope suitable for surface
mounting featuring high avalanche
energy capability, stable blocking
voltage, fast switching and high
thermal cycling performance with low
thermal resistance. Intended for use
in Switched Mode Power Supplies
(SMPS), motor control circuits and
general purpose switching
applications.
QUICK REFERENCE DATA
SYMBOL PARAMETER
V_DS
I_D
P_tot
R_DS(ON)
Drain-source voltage
Drain current (DC)
Total power dissipation
Drain-source on-state resistance
MAX.
200
3.5
50
1.5
UNIT
V
A
W
Ω
PINNING - SOT428
PIN
DESCRIPTION
1 gate
2 drain
3 source
tab drain
PIN CONFIGURATION
tab
2
1
3
SYMBOL
d
g
s
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
I_D
Continuous drain current
I_DM
P_D
∆P_D/∆T_mb
V_GS
V_GSM
E_AS
I_AS
Pulsed drain current
Total dissipation
Linear derating factor
Gate-source voltage
Non-repetitive gate-source
voltage
Single pulse avalanche
energy
Peak avalanche current
T_j, T_stg
Operating junction and
storage temperature range
T_mb = 25 ˚C; V_GS = 10 V
T_mb = 100 ˚C; V_GS = 10 V
T_mb = 25 ˚C
T_mb = 25 ˚C
T_mb > 25 ˚C
t_p ≤ 50 µs
V_DD ≤ 50 V; starting T_j = 25˚C; R_GS = 50 Ω;
V_GS = 5 V
V_DD ≤ 50 V; starting T_j = 25˚C; R_GS = 50 Ω;
V_GS = 5 V
MIN.
-
-
-
-
-
-
-
-
-
- 55
MAX.
3.5
2.5
14
50
0.33
± 15
± 20
25
3.5
175
UNIT
A
A
A
W
W/K
V
V
mJ
A
˚C
THERMAL RESISTANCES
SYMBOL
R_{th j-mb}
R_{th j-a}
PARAMETER
Thermal resistance junction to
mounting base
Thermal resistance junction to
ambient
CONDITIONS
pcb mounted, minimum
footprint
TYP.
-
50
MAX.
3
-
UNIT
K/W
K/W
September 1997
1
Rev 1.000