PHD24N03LT Datasheet, PDF (1/8 Pages) NXP Semiconductors – TrenchMOS transistor Logic level FET

Philips Semiconductors
TrenchMOS transistor
Logic level FET
Preliminary specification
PHD24N03LT
FEATURES
SYMBOL
• ’Trench’ technology
• Very low on-state resistance
• Fast switching
• Stable off-state characteristics
• High thermal cycling performance
• Low thermal resistance
d
g
s
QUICK REFERENCE DATA
V_DSS = 30 V
I_D = 24 A
R_DS(ON) ≤ 56 mΩ (V_GS = 5 V)
R_DS(ON) ≤ 50 mΩ (V_GS = 10 V)
GENERAL DESCRIPTION
N-channel enhancement mode,
logic level, field-effect power
transistor in a plastic envelope
using ’trench’ technology. The
device has very low on-state
resistance. It is intended for use in
dc to dc converters and general
purpose switching applications.
The PHD24N03LT is supplied in the
SOT428 (DPAK) surface mounting
package.
PINNING
PIN
DESCRIPTION
1 gate
2 drain ¹
3 source
tab drain
SOT428 (DPAK)
tab
2
1
3
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
V_DSS
V_DGR
V_GS
I_D
I_DM
P_D
T_j, T_stg
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Continuous drain current
Pulsed drain current
Total power dissipation
Operating junction and
storage temperature
T_j = 25 ˚C to 175˚C
T_j = 25 ˚C to 175˚C; R_GS = 20 kΩ
T_mb = 25 ˚C
T_mb = 100 ˚C
T_mb = 25 ˚C
T_mb = 25 ˚C
MIN.
-
-
-
-
-
-
-
- 55
MAX.
30
30
± 13
24
20
96
60
175
UNIT
V
V
V
A
A
A
W
˚C
THERMAL RESISTANCES
SYMBOL PARAMETER
R_{th j-mb}
R_{th j-a}
Thermal resistance junction
to mounting base
Thermal resistance junction
to ambient
CONDITIONS
pcb mounted, minimum footprint
TYP.
-
50
MAX.
2.5
-
UNIT
K/W
K/W
1 it is not possible to make connection to pin 2 of the SOT428 package.
December 1999
1
Rev 1.100