PHC21025_15 Datasheet, PDF (1/16 Pages) NXP Semiconductors – Complementary intermediate level FET

PHC21025
Complementary intermediate level FET
Rev. 04 — 17 March 2011
Product data sheet
1. Product profile
1.1 General description
Intermediate level N-channel and P-channel complementary pair enhancement mode
Field-Effect Transistor (FET) in a plastic package using vertical D-MOS technology. This
product is designed and qualified for use in computing, communications, consumer and
industrial applications only.
1.2 Features and benefits
„ Low conduction losses due to low
on-state resistance
„ Suitable for high frequency
applications due to fast switching
characteristics
1.3 Applications
„ Motor and actuator drivers
„ Power management
„ Synchronized rectification
1.4 Quick reference data
Table 1.
Symbol
V_DS
Quick reference data
Parameter
drain-source voltage
I_D
drain current
P_tot
total power dissipation
Static characteristics
R_DSon
drain-source on-state
resistance
Conditions
T_j ≥ 25 °C; T_j ≤ 150 °C;
N-channel
T_j ≥ 25 °C; T_j ≤ 150 °C;
P-channel
T_sp ≤ 80 °C; P-channel
T_sp ≤ 80 °C; N-channel
T_amb = 25 °C
Min
-
-
-
-
[1] _-
V_GS = -10 V; I_D = -1 A;
-
T_j = 25 °C; P-channel;
see Figure 16; see Figure 19
V_GS = 10 V; I_D = 2.2 A;
-
T_j = 25 °C; N-channel;
see Figure 15; see Figure 18
Typ Max Unit
-
30 V
-
-30 V
-
-2.3 A
- 3.5 A
-
1
W
0.22 0.25 Ω
0.08 0.1 Ω