PHB42N03LT Datasheet, PDF (1/8 Pages) NXP Semiconductors – TrenchMOS transistor Logic level FET

Philips Semiconductors
TrenchMOS™ transistor
Logic level FET
Product specification
PHB42N03LT
FEATURES
SYMBOL
• ’Trench’ technology
• Very low on-state resistance
• Fast switching
• Stable off-state characteristics
• High thermal cycling performance
• Low thermal resistance
• Surface mounting package
d
g
s
QUICK REFERENCE DATA
V_DSS = 30 V
I_D = 42 A
R_DS(ON) ≤ 26 mΩ (V_GS = 5 V)
R_DS(ON) ≤ 23 mΩ (V_GS = 10 V)
GENERAL DESCRIPTION
N-channel enhancement mode
logic level field-effect power
transistor in a plastic envelope
using ’trench’ technology. The
device has very low on-state
resistance. It is intended for use in
dc to dc converters and general
purpose switching applications.
The PHB42N03LT is supplied in the
SOT404 surface mounting
package.
PINNING
PIN
DESCRIPTION
1 gate
2 drain (no connection
possible)
3 source
tab drain
SOT404
mb
2
13
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
V_DS
V_DGR
±V_GS
I_D
I_D
I_DM
P_tot
T_stg, T_j
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Drain current (DC)
Drain current (DC)
Drain current (pulse peak value)
Total power dissipation
Storage & operating temperature
-
R_GS = 20 kΩ
-
T_mb = 25 ˚C
T_mb = 100 ˚C
T_mb = 25 ˚C
T_mb = 25 ˚C
-
THERMAL RESISTANCES
SYMBOL
R_{th j-mb}
R_{th j-a}
PARAMETER
Thermal resistance junction to
mounting base
Thermal resistance junction to
ambient
CONDITIONS
-
pcb mounted, minimum
footprint
MIN.
-
-
-
-
-
-
-
- 55
MAX.
30
30
15
42
33
168
86
175
TYP.
-
50
MAX.
1.75
-
UNIT
V
V
V
A
A
A
W
˚C
UNIT
K/W
K/W
December 1997
1
Rev 1.300