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PHB11N03LT Datasheet, PDF (1/11 Pages) NXP Semiconductors – N-channel TrenchMOS transistor Logic level FET | |||
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Philips Semiconductors
N-channel TrenchMOS⢠transistor
Logic level FET
Product specification
PHB11N03LT, PHD11N03LT
FEATURES
⢠âTrenchâ technology
⢠Low on-state resistance
⢠Fast switching
⢠Logic level compatible
SYMBOL
d
g
s
QUICK REFERENCE DATA
VDSS = 30 V
ID = 10.5 A
RDS(ON) ⤠150 m⦠(VGS = 5 V)
RDS(ON) ⤠130 m⦠(VGS = 10 V)
GENERAL DESCRIPTION
N-channel enhancement mode, logic level, field-effect power transistor in a plastic envelope using âtrenchâ technology.
Applications:-
⢠d.c. to d.c. converters
⢠switched mode power supplies
The PHB11N03LT is supplied in the SOT404 (D2PAK) surface mounting package.
The PHD11N03LT is supplied in the SOT428 (DPAK) surface mounting package.
PINNING
SOT428 (DPAK)
SOT404 (D2PAK)
PIN
DESCRIPTION
tab
tab
1 gate
2 drain 1
3 source
tab drain
2
1
3
2
13
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
VDSS
VDGR
VGS
VGSM
ID
IDM
PD
Tj, Tstg
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Pulsed gate-source voltage
Continuous drain current
Pulsed drain current
Total power dissipation
Operating junction and
storage temperature
Tj = 25 ËC to 175ËC
Tj = 25 ËC to 175ËC; RGS = 20 kâ¦
Tmb = 25 ËC
Tmb = 100 ËC
Tmb = 25 ËC
Tmb = 25 ËC
MIN.
-
-
-
-
-
-
-
-
- 55
MAX.
30
30
± 15
± 20
10.3
7.3
41
33
175
UNIT
V
V
V
V
A
A
A
W
ËC
1 It is not possible to make contact to pin 2 of the SOT404 or SOT428 package
September 1999
1
Rev 1.000
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