PCA9514A Datasheet, PDF (1/25 Pages) NXP Semiconductors – Hot swappable I2C-bus and SMBus bus buffer

PCA9513A; PCA9514A
Hot swappable I²C-bus and SMBus bus buffer
Rev. 01 — 11 October 2005
Product data sheet
1. General description
The PCA9513A and PCA9514A are hot swappable I²C-bus and SMBus buffers that allow
I/O card insertion into a live backplane without corrupting the data and clock buses.
Control circuitry prevents the backplane from being connected to the card until a stop
command or bus idle occurs on the backplane without bus contention on the card. When
the connection is made, the PCA9513A and PCA9514A provides bidirectional buffering,
keeping the backplane and card capacitances isolated.
Rise time accelerator circuitry allows the use of weaker DC pull-up currents while still
meeting rise time requirements. The PCA9513A and PCA9514A incorporates a digital
ENABLE input pin, which enables the device when asserted HIGH and forces the device
into a Low current mode when asserted LOW, and an open-drain READY output pin,
which indicates that the backplane and card sides are connected together (HIGH) or not
(LOW).
The PCA9513A supplies a 92 µA current source to SCLIN and SDAIN pins in lieu of using
pull-up resistors which is ideal for multidrop bus applications. Including the current source
in the device provides for a consistent RC time constant as cards are removed and
inserted into the backplane. The current source is high-impedance whenever the pin
voltage is greater than the part V_CC.
The PCA9513A and PCA9514A rise time accelerator threshold is 0.8 V to provide better
noise margin over the PCA9511A which is set to 0.6 V.
Remark: The dynamic offset design of the PCA9510A/11A/12A/13A/14A I/O drivers allow
them to be connected to another PCA9510A/11A/12A/13A/14A device in series or in
parallel and to the A side of the PCA9517. The PCA9510A/11A/12A/13A/14A cannot
connect to the static offset I/Os used on the PCA9515/15A/16/16A/18 or PCA9517 B side
or P82B96 Sx/y side.
2. Features
s Bidirectional buffer for SDA and SCL lines increases fanout and prevents SDA and
SCL corruption during live board insertion and removal from multi-point backplane
systems
s Compatible with I²C-bus Standard mode, I²C-bus Fast mode, and SMBus standards
s Built-in ∆V/∆t rise time accelerators on all SDA and SCL lines (0.8 V threshold)
s Rise time accelerator threshold moved from 0.6 V to 0.8 V for improved noise margin
s Active HIGH ENABLE input
s Active HIGH READY open-drain output
s High-impedance SDAn and SCLn pins for V_CC = 0 V