MB2821 Datasheet, PDF (1/9 Pages) NXP Semiconductors – Dual 10-bit D-type flip-flop; positive-edge trigger 3-State

Philips Semiconductors Advanced BiCMOS Products
Dual 10-bit D-type flip-flop;
positive-edge trigger (3-State)
Product specification
MB2821
FEATURES
• 20-bit positive-edge triggered register
• Multiple V_CC and GND pins minimize
switching noise
• Live insertion/extraction permitted
• Power-up reset
• Power-up 3-State
• Output capability: +64mA/–32mA
• Latch-up protection exceeds 500mA per
Jedec JC40.2 Std 17
• ESD protection exceeds 2000V per MIL
STD 883 Method 3015 and 200V per
Machine Model
DESCRIPTION
The MB2821 high-performance BiCMOS
device combines low static and dynamic
power dissipation with high speed and high
output drive.
The MB2821 has two 10-bit, edge triggered
registers, with each register coupled to ten
3-State output buffers. The two sections of
each register are controlled independently by
the clock (nCP) and Output Enable (nOE)
control gates.
Each register is fully edge triggered. The
state of each D input, one set-up time before
the Low-to-High clock transition, is
transferred to the corresponding flip-flop’s Q
output.
The 3-State output buffers are designed to
drive heavily loaded 3-State buses, MOS
memories, or MOS microprocessors.
The active Low Output Enable (nOE) controls
all ten 3-State buffers independent of the
register operation. When nOE is Low, the
data in the register appears at the outputs.
When nOE is High, the outputs are in high
impedance “off” state, which means they will
neither drive nor load the bus.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
t_PLH
t_PHL
C_IN
C_OUT
I_CCZ
Propagation delay
nCP to nQx
Input capacitance
Output capacitance
Total supply current
CONDITIONS
T_amb = 25°C; GND = 0V
C_L = 50pF; V_CC = 5V
V_I = 0V or V_CC
V_O = 0V or V_CC; 3-State
Outputs disabled; V_CC = 5.5V
TYPICAL
4.6
4
7
120
UNIT
ns
pF
pF
µA
ORDERING INFORMATION
PACKAGES
52-pin plastic Quad Flat Pack
TEMPERATURE RANGE
-40°C to +85°C
ORDER CODE
MB2821BB
DRAWING NUMBER
1418B
PIN CONFIGURATION
LOGIC SYMBOL
1Q4 ¹
1Q5 2
È_{1Q6 3}
GND 4
ÈÈ1Q7 5
188 6
1Q9 7
2Q0 8
2Q1 9
2Q2 10
2Q3 11
2Q4 12
2Q5 13
52 51 50 49 48 47 46 45 44 43 42 41 40
MB2821
52–pin PQFP
39 1D4
38 1D5
È_{37 1D6}
36 1D7
ÈÈ_{35 1D8}
34 1D9
33 2D0
32 2D1
31 2D2
30 GND
29 2D3
28 2D4
27 2D5
14 15 16 17 18 19 20 21 22 23 24 25 26
45 44 42 41 39 38 37 36 35 34
1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7 1D8 1D9
46
1CP
47
1OE
1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 1Q8 1Q9
48 49 50 51 1 2 3 5 6 7
33 32 31 29 28 27 25 24 23 22
2D0 2D1 2D2 2D3 2D4 2D5 2D6 2D7 2D8 2D9
21
2CP
20
2OE
2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 2Q8 2Q9
8 9 10 11 12 13 15 16 18 19
August 24, 1993
1
853-1670 10620