LPC81XM_15 Datasheet, PDF(1/77 Page) NXP Semiconductors – 32-bit ARM Cortex-M0+ microcontroller; up to 16 kB flash and 4 kB SRAM

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LPC81XM_15 Datasheet, PDF (1/77 Pages) NXP Semiconductors – 32-bit ARM Cortex-M0+ microcontroller; up to 16 kB flash and 4 kB SRAM

LPC81xM

32-bit ARM Cortex-M0+ microcontroller; up to 16 kB flash and

4 kB SRAM

Rev. 4.4 â 23 June 2015

Product data sheet

1. General description

The LPC81xM are an ARM Cortex-M0+ based, low-cost 32-bit MCU family operating at

CPU frequencies of up to 30 MHz. The LPC81xM support up to 16 kB of flash memory

and 4 kB of SRAM.

The peripheral complement of the LPC81xM includes a CRC engine, one I2C-bus

interface, up to three USARTs, up to two SPI interfaces, one multi-rate timer, self wake-up

timer, and state-configurable timer, one comparator, function-configurable I/O ports

through a switch matrix, an input pattern match engine, and up to 18 general-purpose I/O

pins.

2. Features and benefits

ï® System:

ïµ ARM Cortex-M0+ processor, running at frequencies of up to 30 MHz with

single-cycle multiplier and fast single-cycle I/O port.

ïµ ARM Cortex-M0+ built-in Nested Vectored Interrupt Controller (NVIC).

ïµ System tick timer.

ïµ Serial Wire Debug (SWD) and JTAG boundary scan modes supported.

ïµ Micro Trace Buffer (MTB) supported.

ï® Memory:

ïµ Up to 16 kB on-chip flash programming memory with 64 Byte page write and erase.

ïµ Up to 4 kB SRAM.

ï® ROM API support:

ïµ Boot loader.

ïµ USART drivers.

ïµ I2C drivers.

ïµ Power profiles.

ïµ Flash In-Application Programming (IAP) and In-System Programming (ISP).

ï® Digital peripherals:

ïµ High-speed GPIO interface connected to the ARM Cortex-M0+ IO bus with up to 18

General-Purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors,

programmable open-drain mode, input inverter, and glitch filter.

ïµ High-current source output driver (20 mA) on four pins.

ïµ High-current sink driver (20 mA) on two true open-drain pins.

ïµ GPIO interrupt generation capability with boolean pattern-matching feature on eight

GPIO inputs.

ïµ Switch matrix for flexible configuration of each I/O pin function.

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