LPC2921 Datasheet, PDF (1/81 Pages) NXP Semiconductors – ARM9 microcontroller with CAN, LIN, and USB device

1.
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CAN and LIN, up to 40 kB SRAM, up to 512 kB flash memory, two 10-bit ADCs, and
multiple serial and parallel interfaces in a single chip targeted at consumer, industrial,
medical, communication, and automotive markets. To optimize system power
consumption, the LPC2921/2923/2925 has a very flexible Clock Generation Unit (CGU)
that provides dynamic clock gating and scaling.
2. Features
„ ARM968E-S processor running at frequencies of up to 125 MHz maximum.
„ Multilayer AHB system bus at 125 MHz with four separate layers.
„ On-chip memory:
‹ Two Tightly Coupled Memories (TCM), 16 kB Instruction (ITCM) and 16 kB Data
TCM (DTCM).
‹ On the LPC2925, two separate internal Static RAM (SRAM) instances, 16 kB each.
‹ On the LPC2923 and LPC2921, one 16 kB SRAM block.
‹ 8 kB ETB SRAM, also usable for code execution and data.
‹ Up to 512 kB high-speed flash-program memory.
‹ 16 kB true EEPROM, byte-erasable/programmable.
„ Dual-master, eight-channel GPDMA controller on the AHB multilayer matrix which can
be used with both I²C interfaces, the SPI interfaces, and the UARTs, as well as for
memory-to-memory transfers including the TCM memories.
„ Serial interfaces:
‹ USB 2.0 full-speed device controller with dedicated DMA controller and on-chip
device PHY.
‹ Two-channel CAN controller supporting Full-CAN and extensive message filtering.
‹ Two LIN master controllers with full hardware support for LIN communication. The
LIN interface can be configured as UART to provide two additional UART
interfaces.
‹ Two 550 UARTs with 16-byte Tx and Rx FIFO depths, DMA support, and RS485
(9-bit) support.
‹ Three full-duplex Q-SPIs with four slave-select lines; 16 bits wide; 8 locations deep;
Tx FIFO and Rx FIFO.
‹ Two I²C-bus interfaces.