LPC11U2X Datasheet, PDF(1/67 Page) NXP Semiconductors – 32-bit ARM Cortex-M0 microcontroller; up to 32 kB flash; up to 10 kB SRAM and 4 kB EEPROM; USB device; USART

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

LPC11U2X Datasheet, PDF (1/67 Pages) NXP Semiconductors – 32-bit ARM Cortex-M0 microcontroller; up to 32 kB flash; up to 10 kB SRAM and 4 kB EEPROM; USB device; USART

LPC11U2x

32-bit ARM Cortex-M0 microcontroller; up to 32 kB flash; up

to 10 kB SRAM and 4 kB EEPROM; USB device; USART

Rev. 1 â 29 November 2011

Preliminary data sheet

1. General description

The LPC11U2x are a ARM Cortex-M0 based, low-cost 32-bit MCU family, designed for

8/16-bit microcontroller applications, offering performance, low power, simple instruction

set and memory addressing together with reduced code size compared to existing 8/16-bit

architectures.

The LPC11U2x operate at CPU frequencies of up to 50 MHz.

Equipped with a highly flexible and configurable Full-Speed USB 2.0 device controller, the

LPC11U2x brings unparalleled design flexibility and seamless integration to todayâs

demanding connectivity solutions.

The peripheral complement of the LPC11U2x includes up to 32 kB of flash memory, up to

10 kB of SRAM data memory and 4 kB EEPROM, one Fast-mode Plus I2C-bus interface,

one RS-485/EIA-485 USART with support for synchronous mode and smart card

interface, two SSP interfaces, four general-purpose counter/timers, a 10-bit ADC

(Analog-to-Digital Converter), and up to 54 general-purpose I/O pins.

2. Features and benefits

ï® System:

ïµ ARM Cortex-M0 processor, running at frequencies of up to 50 MHz.

ïµ ARM Cortex-M0 built-in Nested Vectored Interrupt Controller (NVIC).

ïµ Non-Maskable Interrupt (NMI) input selectable from several input sources.

ïµ System tick timer.

ï® Memory:

ïµ Up to 32 kB on-chip flash program memory.

ïµ Up to 4 kB on-chip EEPROM data memory; byte erasable and byte programmable.

ïµ Up to 10 kB SRAM data memory.

ïµ 16 kB boot ROM.

ïµ In-System Programming (ISP) and In-Application Programming (IAP) for flash and

EEPROM via on-chip bootloader software.

ïµ ROM-based USB drivers. Flash updates via USB supported.

ïµ ROM-based 32-bit integer division routines.

ï® Debug options:

ïµ Standard JTAG (Joint Test Action Group) test interface for BSDL (Boundary Scan

Description Language).

ïµ Serial Wire Debug.

▷