ISP1761 Datasheet, PDF (1/158 Pages) NXP Semiconductors – Hi-Speed Universal Serial Bus On-The-Go controller

ISP1761
Hi-Speed Universal Serial Bus On-The-Go controller
Rev. 01 — 12 January 2005
Product data sheet
1. General description
The ISP1761 is a single-chip Hi-Speed Universal Serial Bus (USB) On-The-Go (OTG)
Controller integrated with the advanced Philips Slave Host Controller and the Philips
ISP1582 Peripheral Controller.
The Hi-Speed USB Host Controller and Peripheral Controller comply to Universal Serial
Bus Specification Rev. 2.0 and support data transfer speeds of up to 480 Mbit/s. The
Enhanced Host Controller Interface (EHCI) core implemented in the Host Controller is
adapted from Enhanced Host Controller Interface Specification for Universal Serial Bus
Rev. 1.0. The OTG controller is compliant with On-The-Go Supplement to the USB
Specification Rev. 1.0a.
The ISP1761 has three USB ports. Port 1 can be configured to function as a downstream
port, an upstream port or an OTG port; ports 2 and 3 are always configured as
downstream ports. The OTG port can switch its role from host to peripheral, and
peripheral to host. The OTG port can become a host through the Host Negotiation
Protocol (HNP) as specified in the OTG supplement.
2. Features
s Compliant with Universal Serial Bus Specification Rev. 2.0; supporting data transfer at
high-speed (480 Mbit/s), full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s)
s Integrated Transaction Translator (TT) for Original USB (full-speed and low-speed)
peripheral support
s Three USB ports that support three operational modes:
x Mode 1: Port 1 is an OTG Controller port, and ports 2 and 3 are Host Controller
ports
x Mode 2: Ports 1, 2 and 3 are Host Controller ports
x Mode 3: Port 1 is a Peripheral Controller port, and ports 2 and 3 are Host Controller
ports
s Supports OTG Host Negotiation Protocol (HNP) and Session Request Protocol (SRP)
s Multitasking support with Virtual Segmentation feature (up to four banks)
s High-speed memory controller (variable latency and SRAM external interface)
s Directly addressable memory architecture
s Generic processor interface to most CPUs, such as: Hitachi^® SH-3 and SH-4, Philips
XA, Intel^® StrongARM^®, NEC^® and Toshiba^® MIPS, Motorola^® DragonBall™ and
PowerPC^® Reduced Instruction Set Computer (RISC) processors
s Configurable 32-bit and 16-bit external memory data bus
s Supports Programmed I/O (PIO) and Direct Memory Access (DMA)
s Slave DMA implementation on CPU interface for reducing the host system’s CPU load