IRLZ34N Datasheet, PDF (1/7 Pages) NXP Semiconductors – N-channel enhancement mode Logic level TrenchMOS transistor

Philips Semiconductors
N-channel enhancement mode
Logic level TrenchMOS^TM transistor
Product specification
IRLZ34N
GENERAL DESCRIPTION
N-channel enhancement mode logic
level field-effect power transistor in a
plastic envelope using ’trench’
technology. The device features very
low on-state resistance and has
integral zener diodes giving ESD
protection up to 2kV. It is intended for
use in switched mode power supplies
and general purpose switching
applications.
QUICK REFERENCE DATA
SYMBOL PARAMETER
V_DS
I_D
P_tot
T_j
R_DS(ON)
Drain-source voltage
Drain current (DC)
Total power dissipation
Junction temperature
Drain-source on-state
resistance
V_GS = 10 V
MAX.
55
30
68
175
35
PINNING - TO220AB
PIN
DESCRIPTION
1 gate
2 drain
3 source
tab drain
PIN CONFIGURATION
tab
1 23
SYMBOL
d
g
s
UNIT
V
A
W
˚C
mΩ
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
V_DSS
V_DGR
V_GS
I_D
I_DM
P_D
T_j, T_stg
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Continuous drain current
Pulsed drain current
Total power dissipation
Operating junction and
storage temperature
T_j = 25 ˚C to 175˚C
T_j = 25 ˚C to 175˚C; R_GS = 20 kΩ
T_mb = 25 ˚C
T_mb = 100 ˚C
T_mb = 25 ˚C
T_mb = 25 ˚C
THERMAL RESISTANCES
SYMBOL PARAMETER
R_{th j-mb}
R_{th j-a}
Thermal resistance junction
to mounting base
Thermal resistance junction
to ambient
CONDITIONS
ESD LIMITING VALUE
SYMBOL PARAMETER
V_C
Electrostatic discharge
capacitor voltage, all pins
CONDITIONS
Human body model (100 pF, 1.5 kΩ)
MIN.
-
-
-
-
-
-
-
- 55
MAX.
55
55
± 13
30
21
110
68
175
UNIT
V
V
V
A
A
A
W
˚C
TYP.
-
60
MAX.
2.2
-
UNIT
K/W
K/W
MIN.
-
MAX.
2
UNIT
kV
February 1999
1
Rev 1.000