IRFZ44NS Datasheet, PDF (1/8 Pages) NXP Semiconductors – N-channel enhancement mode TrenchMOS transistor

Philips Semiconductors
N-channel enhancement mode
TrenchMOS^TM transistor
Product specification
IRFZ44NS
GENERAL DESCRIPTION
N-channel enhancement mode
standard level field-effect power
transistor in a surface mounting
plastic envelope using ’trench’
technology. The device features very
low on-state resistance and has
integral zener diodes giving ESD
protection up to 2kV. It is intended for
use in switched mode power supplies
and general purpose switching
applications.
PINNING - SOT404 (D²PAK)
PIN
DESCRIPTION
1 gate
2 drain
3 source
mb drain
QUICK REFERENCE DATA
SYMBOL PARAMETER
V_DS
I_D
P_tot
T_j
R_DS(ON)
Drain-source voltage
Drain current (DC)
Total power dissipation
Junction temperature
Drain-source on-state
resistance
V_GS = 10 V
MAX.
55
49
110
175
22
PIN CONFIGURATION
mb
2
13
SYMBOL
d
g
s
UNIT
V
A
W
˚C
mΩ
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
V_DS
V_DGR
±V_GS
I_D
I_D
I_DM
P_tot
T_stg, T_j
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Drain current (DC)
Drain current (DC)
Drain current (pulse peak value)
Total power dissipation
Storage & operating temperature
-
R_GS = 20 kΩ
-
T_mb = 25 ˚C
T_mb = 100 ˚C
T_mb = 25 ˚C
T_mb = 25 ˚C
-
ESD LIMITING VALUE
SYMBOL
V_C
PARAMETER
Electrostatic discharge capacitor
voltage, all pins
CONDITIONS
Human body model
(100 pF, 1.5 kΩ)
THERMAL RESISTANCES
SYMBOL
R_{th j-mb}
R_{th j-a}
PARAMETER
Thermal resistance junction to
mounting base
Thermal resistance junction to
ambient
CONDITIONS
-
Minimum footprint, FR4
board
MIN.
-
-
-
-
-
-
-
- 55
MAX.
55
55
20
49
35
160
110
175
UNIT
V
V
V
A
A
A
W
˚C
MIN.
-
MAX.
2
UNIT
kV
TYP.
-
50
MAX.
1.4
-
UNIT
K/W
K/W
February 1999
1
Rev 1.000