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| HEF4020BP652 Datasheet, PDF (1/14 Pages) NXP Semiconductors – 14-stage binary counter | |||
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HEF4020B
14-stage binary counter
Rev. 8 â 18 November 2011
Product data sheet
1. General description
The HEF4020B is a 14-stage binary counter with a clock input (CP), an overriding
asynchronous master reset input (MR) and twelve fully buffered outputs (Q0, and Q3 to
Q13). The counter advances on the HIGH to LOW transition of CP. A HIGH on MR clears
all counter stages and forces all outputs LOW, independent of the state of CP. Each
counter stage is a static toggle flip-flop. A feature of the device is its high speed
(typ. 35 MHz at VDD = 15 V).
It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS
(usually ground). Unused inputs must be connected to VDD, VSS, or another input.
2. Features and benefits
ï® High speed operation
ï® Fully static operation
ï® 5 V, 10 V, and 15 V parametric ratings
ï® Standardized symmetrical output characteristics
ï® Specified from ï40 ï°C to +85 ï°C
ï® Complies with JEDEC standard JESD 13-B
3. Ordering information
Table 1. Ordering information
All types operate from ï40 ï°C to +85 ï°C.
Type number Package
Name
Description
HEF4020BP DIP16
plastic dual in-line package; 16 leads (300 mil)
HEF4020BT SO16
plastic small outline package; 16 leads; body width 3.9 mm
Version
SOT38-4
SOT109-1
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