CBTW28DD14ET118 Datasheet, PDF (1/13 Pages) NXP Semiconductors – 14-bit bus switch/multiplexer for DDR2/DDR3/DDR4 applications

CBTW28DD14
14-bit bus switch/multiplexer for DDR2/DDR3/DDR4
applications
Rev. 5 — 28 May 2014
Product data sheet
1. General description
This 14-bit bus switch/multiplexer (MUX) is designed for 1.5 V or 1.8 V supply voltage
operation, POD_12, SSTL_12, SSTL_135, SSTL_15 or SSTL_18 signaling and CMOS
select input levels. It is designed for operation in DDR2, DDR3 or DDR4 memory bus
systems.
The CBTW28DD14 has a 1 : 2 switch or 2 : 1 multiplex topology and offers a 14-bit wide
bus. Each 14-bit wide A-port can be switched to one of two ports B and C, for all bits
simultaneously. The selection of the port is by a simple CMOS input (SELect). Another
CMOS input (ENable) is available to allow all ports to be disconnected. Each port is
non-directional due to the use of FET switches, allowing a multitude of applications
requiring high-bandwidth switching or multiplexing.
The SEL and EN input signals are designed to operate transparently as CMOS input level
signals in both 1.5 V and 1.8 V supply voltage conditions.
CBTW28DD14 uses NXP proprietary high-speed switch architecture providing high
bandwidth, very little insertion loss at low frequency, and very low propagation delay,
allowing use in many applications requiring switching or multiplexing of high-speed
signals. It is available in a 4.5 mm  4.5 mm TFBGA48 package with 0.5 mm ball pitch, for
optimal size versus board layout density considerations. It is characterized for operation
from 10 C to +85 C.
2. Features and benefits
2.1 Topology
 14-bit bus width
 1 : 2 switch/MUX topology
 Bidirectional operation
 Simple CMOS select pin (SEL)
 Simple CMOS enable pin (EN)
2.2 Performance
 2.5 GHz bandwidth
 Low ON insertion loss
 Low crosstalk
 High OFF isolation
 POD_12, SSTL_12, SSTL_135, SSTL_15 or SSTL_18 signaling