BUK582-60A Datasheet, PDF (1/9 Pages) NXP Semiconductors – PowerMOS transistor Logic level FET

Philips Semiconductors
PowerMOS transistor
Logic level FET
Product Specification
BUK582-60A
GENERAL DESCRIPTION
N-channel enhancement mode
logic level field-effect power
transistor in a plastic envelope
suitable for surface mount
applications.
The device is intended for use in
automotive and general purpose
switching applications.
PINNING - SOT223
PIN
DESCRIPTION
1 gate
2 drain
3 source
4 drain (tab)
QUICK REFERENCE DATA
SYMBOL PARAMETER
V_DS
I_D
P_tot
T_j
R_DS(ON)
Drain-source voltage
Drain current (DC)
Total power dissipation
Junction temperature
Drain-source on-state
resistance;
V_GS = 5 V
MAX.
60
2.5
1.7
150
0.15
PIN CONFIGURATION
4
SYMBOL
d
1
2
3
g
s
UNIT
V
A
W
˚C
Ω
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
V_DS
V_DGR
±V_GS
I_D
I_D
I_DM
P_tot
T_stg
T_j
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Drain current (DC)
Drain current (DC)
Drain current (pulse peak value)
Total power dissipation
Storage temperature
Junction Temperature
-
R_GS = 20 kΩ
-
T_amb = 25 ˚C
T_amb = 100 ˚C
T_amb = 25 ˚C
T_amb = 25 ˚C
-
-
MIN.
-
-
-
-
-
-
-
- 55
-
MAX.
60
60
15
2.5
1.5
10
1.7
150
150
UNIT
V
V
V
A
A
A
W
˚C
˚C
THERMAL RESISTANCES
SYMBOL
R_{th j-b}
R_{th j-amb}
PARAMETER
From junction to board¹
From junction to ambient
CONDITIONS
Mounted on any PCB e.g. Fig.18
Mounted on PCB of Fig.18
MIN.
-
-
TYP. MAX. UNIT
40
- K/W
-
75 K/W
1 Temperature measured 1-3 mm from tab.
April 1993
1
Rev 1.000