BUK565-60H Datasheet, PDF (1/8 Pages) NXP Semiconductors – PowerMOS transistor Logic level FET

Philips Semiconductors
PowerMOS transistor
Logic level FET
Product specification
BUK565-60H
GENERAL DESCRIPTION
N-channel enhancement mode logic
level field-effect power transistor in
a plastic envelope suitable for
surface mount applications.
The device is intended for use in
automotive and general purpose
switching applications.
PINNING - SOT404
PIN
DESCRIPTION
1 gate
2 drain
3 source
mb drain
QUICK REFERENCE DATA
SYMBOL PARAMETER
V_DS
I_D
P_tot
T_j
R_DS(ON)
Drain-source voltage
Drain current (DC)
Total power dissipation
Junction temperature
Drain-source on-state
resistance;
V_GS = 5 V
MAX.
60
41
125
175
38
PIN CONFIGURATION
SYMBOL
d
mb
2
13
g
s
UNIT
V
A
W
˚C
mΩ
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
V_DS
V_DGR
±V_GS
±V_GSM
I_D
I_D
I_DM
P_tot
T_stg
T_j
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Non-repetitive gate-source
voltage
Drain current (DC)
Drain current (DC)
Drain current (pulse peak value)
Total power dissipation
Storage temperature
Junction temperature
-
R_GS = 20 kΩ
-
t_p ≤ 50 µs
T_mb = 25 ˚C
T_mb = 100 ˚C
T_mb = 25 ˚C
T_mb = 25 ˚C
-
-
MIN.
-
-
-
-
-
-
-
-
- 55
-
THERMAL RESISTANCES
SYMBOL
R_{th j-mb}
R_{th j-a}
PARAMETER
Thermal resistance junction to
mounting base
Thermal resistance junction to
ambient
CONDITIONS
minimum footprint, FR4 board
(see Fig. 18)
MAX.
60
60
15
20
41
29
164
125
175
175
UNIT
V
V
V
V
A
A
A
W
˚C
˚C
TYP. MAX. UNIT
-
1.2 K/W
50
-
K/W
June 1995
1
Rev 1.000