BUK556-60A Datasheet, PDF (1/7 Pages) NXP Semiconductors – PowerMOS transistor Logic level FET

Philips Semiconductors
PowerMOS transistor
Logic level FET
Product Specification
BUK556-60A
GENERAL DESCRIPTION
N-channel enhancement mode
logic level field-effect power
transistor in a plastic envelope.
The device is intended for use in
Switched Mode Power Supplies
(SMPS), motor control, welding,
DC/DC and AC/DC converters, and
in automotive and general purpose
switching applications.
QUICK REFERENCE DATA
SYMBOL PARAMETER
V_DS
I_D
P_tot
R_DS(ON)
Drain-source voltage
Drain current (DC)
Total power dissipation
Drain-source on-state resistance
V_GS = 5 V
MAX.
60
50
150
26
UNIT
V
A
W
mΩ
PINNING - TO220AB
PIN
DESCRIPTION
1 gate
2 drain
3 source
tab drain
PIN CONFIGURATION
tab
1 23
SYMBOL
d
g
s
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
V_DS
V_DGR
±V_GS
±V_GSM
I_D
I_D
I_DM
P_tot
T_stg
T_j
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Non-repetitive gate-source voltage
Drain current (DC)
Drain current (DC)
Drain current (pulse peak value)
Total power dissipation
Storage temperature
Junction Temperature
-
R_GS = 20 kΩ
-
t_p ≤ 50 µs
T_mb = 25 ˚C
T_mb = 100 ˚C
T_mb = 25 ˚C
T_mb = 25 ˚C
-
-
MIN.
-
-
-
-
-
-
-
-
- 55
-
MAX.
60
60
15
20
50
38
200
150
175
175
UNIT
V
V
V
V
A
A
A
W
˚C
˚C
THERMAL RESISTANCES
SYMBOL
R_{th j-mb}
R_{th j-a}
PARAMETER
Thermal resistance junction to
mounting base
Thermal resistance junction to
ambient
CONDITIONS
MIN. TYP. MAX. UNIT
-
-
1.0 K/W
-
60
- K/W
April 1993
1
Rev 1.100