BUK554-200A Datasheet, PDF (1/7 Pages) NXP Semiconductors – PowerMOS transistor Logic level FET

Philips Semiconductors
PowerMOS transistor
Logic level FET
Product Specification
BUK554-200A/B
GENERAL DESCRIPTION
N-channel enhancement mode
logic level field-effect power
transistor in a plastic envelope.
The device is intended for use in
Switched Mode Power Supplies
(SMPS), motor control, welding,
DC/DC and AC/DC converters, and
in automotive and general purpose
switching applications.
PINNING - TO220AB
PIN
DESCRIPTION
1 gate
2 drain
3 source
tab drain
QUICK REFERENCE DATA
SYMBOL PARAMETER
V_DS
I_D
P_tot
T_j
R_DS(ON)
BUK554
Drain-source voltage
Drain current (DC)
Total power dissipation
Junction temperature
Drain-source on-state
resistance;
V_GS = 5 V
MAX.
-200A
200
9.2
90
175
0.4
PIN CONFIGURATION
SYMBOL
tab
MAX.
-200B
200
8.2
90
175
0.5
d
UNIT
V
A
W
˚C
Ω
1 23
g
s
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
MIN.
V_DS
Drain-source voltage
-
-
V_DGR
Drain-gate voltage
R_GS = 20 kΩ
-
±V_GS
Gate-source voltage
-
-
±V_GSM
Non-repetitive gate-source voltage t_p ≤ 50 µs
-
I_D
Drain current (DC)
T_mb = 25 ˚C
-
I_D
Drain current (DC)
T_mb = 100 ˚C
-
I_DM
Drain current (pulse peak value) T_mb = 25 ˚C
-
P_tot
Total power dissipation
T_stg
Storage temperature
T_j
Junction Temperature
T_mb = 25 ˚C
-
-
- 55
-
-
THERMAL RESISTANCES
SYMBOL
R_{th j-mb}
R_{th j-a}
PARAMETER
Thermal resistance junction to
mounting base
Thermal resistance junction to
ambient
CONDITIONS
MAX.
200
200
15
20
-200A
9.2
6.5
36
-200B
8.2
5.8
33
90
175
175
UNIT
V
V
V
V
A
A
A
W
˚C
˚C
MIN. TYP. MAX. UNIT
-
- 1.67 K/W
-
60
- K/W
April 1993
1
Rev 1.100