BUK543-100A Datasheet, PDF (1/8 Pages) NXP Semiconductors – PowerMOS transistor Logic level FET

Philips Semiconductors
PowerMOS transistor
Logic level FET
Product Specification
BUK543-100A/B
GENERAL DESCRIPTION
N-channel enhancement mode
logic level field-effect power
transistor in a plastic full-pack
envelope.
The device is intended for use in
Switched Mode Power Supplies
(SMPS), motor control, welding,
DC/DC and AC/DC converters, and
in automotive and general purpose
switching applications.
QUICK REFERENCE DATA
SYMBOL PARAMETER
V_DS
I_D
P_tot
R_DS(ON)
BUK543
Drain-source voltage
Drain current (DC)
Total power dissipation
Drain-source on-state
resistance;
V_GS = 5 V
MAX.
-100A
100
8.3
25
0.18
MAX.
-100B
100
7.5
25
0.22
UNIT
V
A
W
Ω
PINNING - SOT186
PIN
DESCRIPTION
1 gate
2 drain
3 source
case isolated
PIN CONFIGURATION
case
12 3
SYMBOL
d
g
s
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
MIN.
V_DS
Drain-source voltage
-
-
V_DGR
Drain-gate voltage
R_GS = 20 kΩ
-
±V_GS
Gate-source voltage
-
-
±V_GSM
Non-repetitive gate-source voltage t_p ≤ 50 µs
-
I_D
Drain current (DC)
T_hs = 25 ˚C
-
I_D
Drain current (DC)
T_hs = 100 ˚C
-
I_DM
Drain current (pulse peak value) T_hs = 25 ˚C
-
P_tot
Total power dissipation
T_stg
Storage temperature
T_j
Junction Temperature
T_hs = 25 ˚C
-
-
- 55
-
-
THERMAL RESISTANCES
SYMBOL
R_{th j-hs}
R_{th j-a}
PARAMETER
Thermal resistance junction to
heatsink
Thermal resistance junction to
ambient
CONDITIONS
with heatsink compound
MAX.
100
100
15
20
-100A
8.3
5.2
33
-100B
7.5
4.7
30
25
150
150
UNIT
V
V
V
V
A
A
A
W
˚C
˚C
MIN. TYP. MAX. UNIT
-
-
5.0 K/W
-
55
- K/W
April 1993
1
Rev 1.100