87C54 Datasheet, PDF (1/21 Pages) Intel Corporation – CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER WITH 16 KBYTES USER PROGRAMMABLE EPROM

Philips Semiconductors
CMOS single-chip 8-bit microcontrollers
Preliminary specification
87C54/87C58
DESCRIPTION
The 87C54/87C58 Single-Chip 8-Bit Microcontroller is manufactured
in an advanced CMOS process and is a derivative of the 80C51
microcontroller family. The 87C54/87C58 has the same instruction
set as the 80C51.
This device provides architectural enhancements that make it
applicable in a variety of applications for general control systems.
The 87C58 contains 32k × 8 EPROM memory, and the 87C54
contains 16k × 8 EPROM memory, a volatile 256 × 8 read/write data
memory, four 8-bit I/O ports, three 16-bit timer/event counters, a
multi-source, two-priority-level, nested interrupt structure, an
enhanced UART and on-chip oscillator and timing circuits. For
systems that require extra capability, the 87C54/87C58 can be
expanded using standard TTL compatible memories and logic.
Its added features make it an even more powerful microcontroller for
applications that require pulse width modulation, high-speed I/O and
up/down counting capabilities such as motor control. It also has a
more versatile serial channel that facilitates multiprocessor
communications.
See 80C52/54/58 datasheet for ROM device specification.
FEATURES
• 80C51 central processing unit
• 16k × 8 EPROM expandable externally to 64k bytes (87C54)
• 16k × 8 EPROM (87C54) and
32k × 8 EPROM expandable externally to 64k bytes (87C58)
– Improved Quick Pulse programming algorithm
– Two level program security system
– 32 byte encryption array
• 256 × 8 RAM, expandable externally to 64k bytes
• Three 16-bit timer/counters
– T2 is an up/down counter
• Four 8-bit I/O ports
• Full-duplex enhanced UART
– Framing error detection
– Automatic address recognition
• Power control modes
– Idle mode
– Power-down mode
• Once (On Circuit Emulation) Mode
• Five package styles
• OTP package available
• Programmable clock out
• 6 interrupt sources
• 2 level priority
PIN CONFIGURATIONS
T2/P1.0 1
T2EX/P1.1 2
P1.2 3
P1.3 4
P1.4 5
P1.5 6
P1.6 7
P1.7 8
RST 9
RxD/P3.0 10
TxD/P3.1 11
INT0/P3.2 12
INT1/P3.3 13
T0/P3.4 14
T1/P3.5 15
WR/P3.6 16
RD/P3.7 17
XTAL2 18
XTAL1 19
V_SS 20
40 V_CC
39 P0.0/AD0
38 P0.1/AD1
37 P0.2/AD2
36 P0.3/AD3
35 P0.4/AD4
34 P0.5/AD5
33 P0.6/AD6
32 P0.7/AD7
DUAL
IN-LINE
PACKAGE
31 EA/V_PP
30 ALE/PROG
29 PSEN
28 P2.7/A15
27 P2.6/A14
26 P2.5/A13
25 P2.4/A12
24 P2.3/A11
23 P2.2/A10
22 P2.1/A9
21 P2.0/A8
SU00748
1996 Aug 16
3-215