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87C51FA Datasheet, PDF (1/1 Pages) Intel Corporation – CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER
Philips Semiconductors
CMOS single-chip 8-bit microcontrollers
Product specification
87C51FA/87C51FB
DESCRIPTION
The 87C51FA and 87C51FB Single-Chip 8-Bit Microcontrollers are
manufactured in an advanced CMOS process and are derivatives of
the 80C51 microcontroller family. The 87C51FA/FB has the same
instruction set as the 80C51.
This device provides architectural enhancements that make it
applicable in a variety of applications for general control systems.
The 87C51FA contains 8k × 8 memory, and the 87C51FB contains
16k × 8 memory. They both contain a volatile 256 × 8 read/write data
memory, four 8-bit I/O ports, three 16-bit timer/event counters, a
Programmable Counter Array (PCA), a multi-source,
two-priority-level, nested interrupt structure, an enhanced UART and
on-chip oscillator and timing circuits. For systems that require extra
capability, the 87C51FA/FB can be expanded using standard TTL
compatible memories and logic.
Its added features make it an even more powerful microcontroller for
applications that require pulse width modulation, high-speed I/O and
up/down counting capabilities such as motor control. It also has a
more versatile serial channel that facilitates multiprocessor
communications.
See 83C51FA/83C51FB/83C51FC/80C51FA datasheet for ROM
and ROMless devices.
FEATURES
• 80C51 central processing unit
• 87C51FA: 8k × 8 EPROM
87C51FB: 16k × 8 EPROM
– expandable externally to 64k bytes
– Quick Pulse programming algorithm
– Two level program security system
• 256 × 8 RAM, expandable externally to 64k bytes
• Three 16-bit timer/counters
– T2 is an up/down counter
• Programmable Counter Array (PCA)
– High speed output
– Capture/compare
– Pulse Width Modulator
– Watchdog Timer
• Four 8-bit I/O ports
• Full-duplex enhanced UART
– Framing error detection
– Automatic address recognition
• Power control modes
– Idle mode
– Power-down mode
• Once (On Circuit Emulation) Mode
• Five package styles
• OTP package available
PIN CONFIGURATIONS
T2/P1.0 1
T2EX/P1.1 2
ECI/P1.2 3
CEX0/P1.3 4
CEX1/P1.4 5
CEX2/P1.5 6
CEX3/P1.6 7
CEX4/P1.7 8
RST 9
RxD/P3.0 10
TxD/P3.1 11
INT0/P3.2 12
INT1/P3.3 13
T0/P3.4 14
T1/P3.5 15
WR/P3.6 16
RD/P3.7 17
XTAL2 18
XTAL1 19
VSS 20
40 VCC
39 P0.0/AD0
38 P0.1/AD1
37 P0.2/AD2
36 P0.3/AD3
35 P0.4/AD4
34 P0.5/AD5
33 P0.6/AD6
32 P0.7/AD7
DUAL
IN-LINE
PACKAGE
31 EA
30 ALE
29 PSEN
28 P2.7/A15
27 P2.6/A14
26 P2.5/A13
25 P2.4/A12
24 P2.3/A11
23 P2.2/A10
22 P2.1/A9
21 P2.0/A8
SU00714A
1996 Aug 16
3-61
853–1692 17199