74LVT373 Datasheet, PDF (1/6 Pages) NXP Semiconductors – 3.3 Volt ABT octal transparent latch 3-State

Philips Semiconductors Low Voltage Products
3.3 Volt ABT octal transparent latch (3–State)
Objective specification
74LVT373
FEATURES
• Designed for use in the 3.3V
high–performance market
• Supports mixed–mode signal operation; 5V
input and output voltages with 3.3V V_CC
• Bus–hold inputs eliminate the need for
external pull-up resistors to hold unused
pins
• Live insertion/extraction permitted
• No bus current loading when output is tied
to 5V bus
• 8–bit transparent latch
• 3-State output buffers
• Zero-static power dissipation
• Pin and function compatibility with ABT
• AC and DC performance compatibility with
ABT
• Latch–up protection exceeds 500mA per
JEDEC JC40.2 Std 17
• ESD protection exceeds 2000 V per MIL
STD 883 Method 3015 and 200 V per
Machine Model
DESCRIPTION
The 74LVT373 device is designed specifically
for low–voltage (3.3V) V_CC operation, but can
provide a TTL interface to a 5V system
environment.
The 74LVT373 high-performance BiCMOS
device combines zero static and low dynamic
power dissipation with high speed and high
output drive.
The 74LVT373 device is an octal transparent
latch coupled to eight 3-State output buffers.
The two sections of the device are controlled
independently by Enable (E) and Output
Enable (OE) control gates.
The data on the D inputs are transferred to
the latch outputs when the Latch Enable (E)
input is High. The latch remains transparent
to the data inputs while E is High, and stores
the data that is present one setup time before
the High-to-Low enable transition.
The 3-State output buffers are designed to
drive heavily loaded 3-State buses, MOS
memories, or MOS microprocessors. The
active-Low Output Enable (OE) controls all
eight 3-State buffers independent of the latch
operation.
When OE is Low, the latched or transparent
data appears at the outputs. When OE is
High, the outputs are in the High-impedance
”OFF” state, which means they will neither
drive nor load the bus.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
t_PLH
t_PHL
C_IN
C_OUT
I_CCZ
Propagation delay
Dn to Qn
Input capacitance
Output capacitance
Total supply current
CONDITIONS
T_amb = 25°C; GND = 0V
C_L = 50pF; V_CC = 5V
V_I = 0V or V_CC
V_I = 0V or V_CC
Outputs disabled; V_CC =5.5V
TYPICAL
4.2
4
7
50
UNIT
ns
pF
pF
µA
ORDERING INFORMATION
PACKAGES
20–Pin Plastic SOL
20–Pin Plastic SSOP
20–Pin Plastic TSSOP
TEMPERATURE RANGE
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
ORDER CODE
74LVT373D
74LVT373DB
74LVT373PW
PIN DESCRIPTION
PIN NUMBER
1
3, 4, 7, 8, 13, 14, 17, 18
2, 5, 6, 9, 12, 15, 16, 19
11
10
20
SYMBOL
OE
D0-D7
Q0-Q7
E
GND
V_CC
Output enable input (active-Low)
Data inputs
Data outputs
Enable input (active-High)
Ground (0V)
Positive supply voltage
FUNCTION
DRAWING NUMBER
0172D
1640B
TBD
July 1993
2