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74LVT16500A_06 Datasheet, PDF (1/19 Pages) NXP Semiconductors – 3.3 V 18-bit universal bus transceiver; 3-state | |||
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74LVT16500A
3.3 V 18-bit universal bus transceiver; 3-state
Rev. 03 â 29 May 2006
Product data sheet
1. General description
The 74LVT16500A is a high-performance BiCMOS product designed for VCC operation at
3.3 V.
This device is an 18-bit universal transceiver featuring non-inverting 3-state bus
compatible outputs in both send and receive directions. Data ï¬ow in each direction is
controlled by output enable (OEAB and OEBA), latch enable (LEAB and LEBA), and clock
(CPAB and CPBA) inputs. For A-to-B data ï¬ow, the device operates in the transparent
mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CPAB is held at a
HIGH or LOW logic level. If LEAB is LOW, the A-bus data is stored in the latch/ï¬ip-ï¬op on
the HIGH-to-LOW transition of CPAB. When OEAB is HIGH, the outputs are active. When
OEAB is LOW, the outputs are in the high-impedance state.
Data ï¬ow for B-to-A is similar to that of A-to-B but uses OEBA, LEBA and CPBA. The
output enables are complimentary (OEAB is active HIGH, and OEBA is active LOW).
Active bus-hold circuitry is provided to hold unused or ï¬oating data inputs at a valid logic
level.
2. Features
I 18-bit bidirectional bus interface
I 3-state buffers
I Output capability: +64 mA and â32 mA
I TTL input and output switching levels
I Input and output interface capability to systems at 5 V supply
I Bus-hold data inputs eliminate the need for external pull-up resistors to hold unused
inputs
I Live insertion/extraction permitted
I Power-up reset
I Power-up 3-state
I No bus current loading when output is tied to 5 V bus
I Negative edge-triggered clock inputs
I Latch-up protection:
N JESD78: exceeds 500 mA
I ESD protection:
N MIL STD 883 Method 3015: exceeds 2000 V
N CDM JESD22-C101-C exceeds 1000 V
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