74LVC_LVCH16373A_15 Datasheet, PDF(1/17 Page) NXP Semiconductors – 16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

74LVC_LVCH16373A_15 Datasheet, PDF (1/17 Pages) NXP Semiconductors – 16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state

74LVC16373A; 74LVCH16373A

16-bit D-type transparent latch with 5 V tolerant

inputs/outputs; 3-state

Rev. 8 â 6 January 2014

Product data sheet

1. General description

The 74LVC16373A and 74LVCH16373A are 16-bit D-type transparent latches featuring

separate D-type inputs with bus hold (74LVCH16373A only) for each latch and 3-state

outputs for bus-oriented applications. One Latch Enable (LE) input and one Output Enable

(OE) are provided for each octal. Inputs can be driven from either 3.3 V or 5 V devices.

When disabled, up to 5.5 V can be applied to the outputs. These features allow the use of

these devices in mixed 3.3 V and 5 V applications.

The device consists of two sections of eight D-type transparent latches with 3-state true

outputs. When LE is HIGH, data at the Dn inputs enter the latches. In this condition, the

latches are transparent, that is, the latch outputs change each time its corresponding

D-input changes. The latches store the information that was present at the D-inputs one

set-up time (tsu) preceding the HIGH-to-LOW transition of LE. When OE is LOW, the

contents of the eight latches are available at the outputs. When OE is HIGH, the outputs

go to the high impedance OFF-state. Operation of the OE input does not affect the state of

the latches. Bus hold on the data inputs eliminates the need for external pull-up resistors

to hold unused inputs.

2. Features and benefits

ï® 5 V tolerant inputs/outputs for interfacing with 5 V logic

ï® Wide supply voltage range from 1.2 V to 3.6 V

ï® CMOS low power consumption

ï® Multibyte flow-through standard pinout architecture

ï® Multiple low inductance supply pins for minimum noise and ground bounce

ï® Direct interface with TTL levels

ï® All data inputs have bus hold (74LVCH16373A only)

ï® High-impedance when VCC = 0 V

ï® Complies with JEDEC standard:

ïµ JESD8-7A (1.65 V to 1.95 V)

ïµ JESD8-5A (2.3 V to 2.7 V)

ïµ JESD8-C/JESD36 (2.7 V to 3.6 V)

ï® ESD protection:

ïµ HBM JESD22-A114F exceeds 2000 V

ïµ MM JESD22-A115-B exceeds 200 V

ïµ CDM JESD22-C101E exceeds 1000 V

ï® Specified from ï40 ï°C to +85 ï°C and ï40 ï°C to +125 ï°C

▷