74LVCH32244A_15 Datasheet, PDF (1/14 Pages) NXP Semiconductors – 32-bit buffer/line driver; 5 V input/output tolerant; 3-state

74LVCH32244A
32-bit buffer/line driver; 5 V input/output tolerant; 3-state
Rev. 3 — 16 December 2011
Product data sheet
1. General description
The 74LVCH32244A is a high-performance, low-power, low-voltage, Si-gate CMOS
device and superior to most advanced CMOS compatible TTL families. Inputs can be
driven from either 3.3 V or 5.0 V devices. In 3-state operation outputs can handle 5 V.
These features allow the use of these devices as translators in a mixed 3.3 V and 5 V
environment.
The 74LVCH32244A is a 32-bit non-inverting buffer/line driver with 3-state outputs. The
3-state outputs are controlled by eight output enable outputs (1OE to 8OE). A HIGH on pin
nOE causes the outputs to assume a high-impedance OFF-state.
To ensure the high-impedance state during power-up or power-down, pin nOE should be
tied to V_CC through a pull-up resistor; the minimum value of the resistor is determined by
the current-sinking capability of the driver.
Bus hold on data inputs eliminates the need for external pull-up resistors to hold unused
or floating data inputs at a valid logic level.
2. Features and benefits
 5 V tolerant inputs/outputs for interfacing with 5 V logic
 Wide supply voltage range from 1.2 V to 3.6 V
 CMOS low-power consumption
 MULTIBYTE flow-through standard pinout architecture
 Low inductance multiple power and ground pins for minimum noise and ground
bounce
 Direct interface with TTL levels
 Inputs accept voltages up to 5.5 V
 All data inputs have bus hold
 Complies with JEDEC standard:
 JESD8-7A (1.65 V to 1.95 V)
 JESD8-5A (2.3 V to 2.7 V)
 JESD8-C/JESD36 (2.7 V to 3.6 V)
 ESD protection:
 HBM JESD22-A114F exceeds 2000 V
 MM JESD22-A115-B exceeds 200 V
 CDM JESD22-C101E exceeds 1000 V
 Specified from 40 C to +85 C
 Packaged in plastic fine-pitch ball grid array package