74LVC1G332 Datasheet, PDF (1/15 Pages) NXP Semiconductors – Single 3-input OR gate

74LVC1G332
Single 3-input OR gate
Rev. 01 — 11 October 2006
Product data sheet
1. General description
The 74LVC1G332 is a high-performance, low-power, low-voltage, Si-gate CMOS device,
superior to most advanced CMOS compatible TTL families.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these
devices as translators in mixed 3.3 V and 5 V applications.
Schmitt trigger action at all inputs makes the circuit tolerant of slower input rise and fall
time.
This device is fully specified for partial power-down applications using I_OFF.
The I_OFF circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
The 74LVC1G332 provides one 3-input OR function.
2. Features
I Wide supply voltage range from 1.65 V to 5.5 V
I High noise immunity
I Complies with JEDEC standard:
N JESD8-7 (1.65 V to 1.95 V)
N JESD8-5 (2.3 V to 2.7 V)
N JESD8B/JESD36 (2.7 V to 3.6 V)
I ±24 mA output drive (V_CC = 3.0 V)
I CMOS low power consumption
I Latch-up performance exceeds 250 mA
I Direct interface with TTL levels
I Inputs accept voltages up to 5 V
I ESD protection:
N HBM JESD22-A114-D exceeds 2000 V
N MM JESD22-A115-A exceeds 200 V
N CDM JESD22-C101-C exceeds 1000 V
I Multiple package options
I Specified from −40 °C to +85 °C and −40 °C to +125 °C