74LVC1G123 Datasheet, PDF (1/31 Pages) NXP Semiconductors – Single retriggerable monostable multivibrator

74LVC1G123
Single retriggerable monostable multivibrator; Schmitt trigger
inputs
Rev. 4 — 27 November 2013
Product data sheet
1. General description
The 74LVC1G123 is a single retriggerable monostable multivibrator with Schmitt trigger
inputs. Output pulse width is controlled by three methods:
1. The basic pulse is programmed by selection of an external resistor (R_EXT) and
capacitor (C_EXT).
2. Once triggered, the basic output pulse width may be extended by retriggering the
gated active LOW-going edge input (A) or the active HIGH-going edge input (B). By
repeating this process, the output pulse period (Q = HIGH) can be made as long as
desired. Alternatively an output delay can be terminated at any time by a LOW-going
edge on input CLR, which also inhibits the triggering.
3. An internal connection from CLR to the input gates makes it possible to trigger the
circuit by a HIGH-going signal at input CLR.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these
devices as translators in a mixed 3.3 V and 5 V environment. Schmitt trigger inputs,
makes the circuit highly tolerant to slower input rise and fall times.
This device is fully specified for partial power-down applications using I_OFF. The I_OFF
circuitry disables the output, preventing the damaging backflow current through the device
when it is powered down.
2. Features and benefits
 Wide supply voltage range from 1.65 V to 5.5 V
 High noise immunity
 24 mA output drive (V_CC = 3.0 V)
 CMOS low power consumption
 DC triggered from active HIGH or active LOW inputs
 Retriggerable for very long pulses up to 100 % duty factor
 Direct reset terminates output pulse
 Schmitt trigger on all inputs
 Complies with JEDEC standard:
 JESD8-7 (1.65 V to 1.95 V)
 JESD8-5 (2.3 V to 2.7 V)
 JESD8-B/JESD36 (2.7 V to 3.6 V)
 Power-on-reset on outputs
 Latch-up performance exceeds 100 mA
 Direct interface with TTL levels