74LVC1G06_15 Datasheet, PDF (1/18 Pages) NXP Semiconductors – Inverter with open-drain output

74LVC1G06
Inverter with open-drain output
Rev. 10 — 29 June 2012
Product data sheet
1. General description
The 74LVC1G06 provides the inverting buffer.
Input can be driven from either 3.3 V or 5 V devices. These features allow the use of
these devices in a mixed 3.3 V and 5 V environment.
Schmitt-trigger action at all inputs makes the circuit tolerant for slower input rise and fall
time.
This device is fully specified for partial power-down applications using I_OFF.
The I_OFF circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
The output of the device is an open drain and can be connected to other open-drain
outputs to implement active-LOW wired-OR or active-HIGH wired-AND functions.
2. Features and benefits
 Wide supply voltage range from 1.65 V to 5.5 V
 High noise immunity
 Complies with JEDEC standard:
 JESD8-7 (1.65 V to 1.95 V)
 JESD8-5 (2.3 V to 2.7 V)
 JESD8B/JESD36 (2.7 V to 3.6 V)
 24 mA output drive (V_CC = 3.0 V)
 CMOS low power consumption
 Latch-up performance exceeds 250 mA
 Direct interface with TTL levels
 Inputs accept voltages up to 5 V
 Multiple package options
 ESD protection:
 HBM JESD22-A114F exceeds 2000 V
 MM JESD22-A115-A exceeds 200 V
 Specified from 40 C to +125 C