|
74LVC1G04_15 Datasheet, PDF (1/19 Pages) NXP Semiconductors – Single inverter | |||
|
74LVC1G04
Single inverter
Rev. 12 â 6 August 2012
Product data sheet
1. General description
The 74LVC1G04 provides one inverting buffer.
Input can be driven from either 3.3 V or 5 V devices. These features allow the use of
these devices in a mixed 3.3 V and 5 V environment.
Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall
time.
This device is fully specified for partial power-down applications using IOFF. The IOFF
circuitry disables the output, preventing the damaging backflow current through the device
when it is powered down.
2. Features and benefits
ï® Wide supply voltage range from 1.65 V to 5.5 V
ï® 5 V tolerant inputs for interfacing with 5 V logic
ï® High noise immunity
ï® Complies with JEDEC standard:
ïµ JESD8-7 (1.65 V to 1.95 V)
ïµ JESD8-5 (2.3 V to 2.7 V)
ïµ JESD8-B/JESD36 (2.7 V to 3.6 V)
ï® ESD protection:
ïµ HBM JESD22-A114F exceeds 2000 V
ïµ MM JESD22-A115-A exceeds 200 V
ï® ï±24 mA output drive (VCC = 3.0 V)
ï® CMOS low power consumption
ï® Latch-up performance exceeds 250 mA
ï® Direct interface with TTL levels
ï® Inputs accept voltages up to 5 V
ï® Multiple package options
ï® Specified from ï40 ï°C to +85 ï°C and ï40 ï°C to +125 ï°C.
|
▷ |