74LV595_15 Datasheet, PDF (1/20 Pages) NXP Semiconductors – 8-bit serial-in/serial-out or parallel-out shift register; 3-state

74LV595
8-bit serial-in/serial-out or parallel-out shift register; 3-state
Rev. 03 — 21 April 2009
Product data sheet
1. General description
The 74LV595 is an 8 stage serial shift register with a storage register and 3-state outputs.
Both the shift and storage register have separate clocks. It is a low-voltage Si-gate CMOS
device and is pin and functionally compatible with the 74HC595 and 74HCT595.
Data is shifted on the positive-going transitions of the SHCP input. The data in the shift
register is transferred to the storage register on a positive-going transition of the STCP
input. If both clocks are connected together, the shift register will always be one clock
pulse ahead of the storage register.
The shift register has a serial input (DS) and a serial output (Q7S) for cascading the
device. It is also provided with an asynchronous reset input MR (active LOW) for all 8 shift
register stages. The storage register has 8 parallel 3-state bus driver outputs. Data in the
storage register appears at the output whenever the output enable input (OE) is LOW.
2. Features
I Optimized for low voltage applications: 1.0 V to 3.6 V
I Accepts TTL input levels between V_CC = 2.7 V and V_CC = 3.6 V
I Typical output ground bounce < 0.8 V at V_CC = 3.3 V and T_amb = 25 °C
I Typical HIGH-level output voltage (V_OH) undershoot: > 2 V at V_CC = 3.3 V and
T_amb = 25 °C
I Specified from −40 °C to +85 °C and from −40 °C to +125 °C
I Has a shift register with direct clear
I Multiple package options
I Output capability:
N Parallel outputs; bus driver
N serial output; standard
I ESD protection:
N HBM JESD22-A114E exceeds 2000 V
N MM JESD22-A115-A exceeds 200 V
3. Applications
I Serial-to-parallel data conversion
I Remote control holding register