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| 74LV4053_15 Datasheet, PDF (1/27 Pages) NXP Semiconductors – Triple single-pole double-throw analog switch | |||
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74LV4053
Triple single-pole double-throw analog switch
Rev. 5 â 18 September 2014
Product data sheet
1. General description
The 74LV4053 is a triple single-pole double-throw (SPDT) analog switch, suitable for use
as an analog or digital multiplexer/demultiplexer. It is a low-voltage Si-gate CMOS device
and is pin and function compatible with the 74HC4053 and 74HCT4053. Each switch has
a digital select input (Sn), two independent inputs/outputs (nY0 and nY1) and a common
input/output (nZ). All three switches share an enable input (E). A HIGH on E causes all
switches into the high-impedance OFF-state, independent of Sn.
VCC and GND are the supply voltage connections for the digital control inputs (Sn and E).
The VCC to GND range is 1 V to 6 V. The analog inputs/outputs (nY0, nY1 and nZ) can
swing between VCC as a positive limit and VEE as a negative limit. VCC ï VEE may not
exceed 6 V. For operation as a digital multiplexer/demultiplexer, VEE is connected to GND
(typically ground). VEE and VSS are the supply voltage connections for the switches.
2. Features and benefits
ï® Optimized for low-voltage applications: 1.0 V to 3.6 V
ï® Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V
ï® Low ON resistance:
ïµ 180 ï (typical) at VCC ï VEE = 2.0 V
ïµ 100 ï (typical) at VCC ï VEE = 3.0 V
ïµ 75 ï (typical) at VCC ï VEE = 4.5 V
ï® Logic level translation:
ïµ To enable 3 V logic to communicate with ï±3 V analog signals
ï® Typical âbreak before makeâ built in
ï® ESD protection:
ïµ HBM JESD22-A114-C exceeds 2000 V
ïµ MM JESD22-A115-A exceeds 200 V
ï® Multiple package options
ï® Specified from ï40 ï°C to +85 ï°C and from ï40 ï°C to +125 ï°C
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