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| 74LV4051_15 Datasheet, PDF (1/27 Pages) NXP Semiconductors – 8-channel analog multiplexer/demultiplexer | |||
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74LV4051
8-channel analog multiplexer/demultiplexer
Rev. 5 â 17 September 2014
Product data sheet
1. General description
The 74LV4051 is an 8-channel analog multiplexer/demultiplexer with three digital select
inputs (S0 to S2), an active-LOW enable input (E), eight independent inputs/outputs (Y0 to
Y7) and a common input/output (Z). It is a low-voltage Si-gate CMOS device that is pin
and function compatible with 74HC4051 and 74HCT4051. With E LOW, one of the eight
switches is selected (low impedance ON-state) by S0 to S2. With E HIGH, all switches are
in the high-impedance OFF-state, independent of S0 to S2.
VCC and GND are the supply voltage pins for the digital control inputs (S0 to S2, and E).
The VCC to GND ranges are 1.0 V to 6.0 V. The analog inputs/outputs (Y0 to Y7, and Z)
can swing between VCC as a positive limit and VEE as a negative limit. VCC ï VEE may not
exceed 6.0 V. For operation as a digital multiplexer/demultiplexer, VEE is connected to
GND (typically ground).
2. Features and benefits
ï® Optimized for low-voltage applications: 1.0 V to 6.0 V
ï® Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V
ï® Low ON resistance:
ïµ 145 ï (typical) at VCC ï VEE = 2.0 V
ïµ 80 ï (typical) at VCC ï VEE = 3.0 V
ïµ 60 ï (typical) at VCC ï VEE = 4.5 V
ï® Logic level translation:
ïµ To enable 3 V logic to communicate with ï±3 V analog signals
ï® Typical âbreak before makeâ built in
ï® ESD protection:
ïµ HBM JESD22-A114E exceeds 2000 V
ïµ MM JESD22-A115-A exceeds 200 V
ï® Multiple package options
ï® Specified from ï40 ï°C to +85 ï°C and from ï40 ï°C to +125 ï°C
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