74LV164_15 Datasheet, PDF (1/21 Pages) NXP Semiconductors – 8-bit serial-in/parallel-out shift register

74LV164
8-bit serial-in/parallel-out shift register
Rev. 03 — 4 February 2005
Product data sheet
1. General description
The 74LV164 is a low-voltage, Si-gate CMOS device and is pin and function compatible
with the 74HC164 and 74HCT164.
The 74LV164 is an 8-bit edge-triggered shift register with serial data entry and an output
from each of the eight stages. Data is entered serially through one of two inputs (DSA or
DSB) and either input can be used as an active HIGH enable for data entry through the
other input. Both inputs must be connected together or an unused input must be tied
HIGH.
Data shifts one place to the right on each LOW-to-HIGH transition of the clock input (CP)
and enters into Q0, which is the logical AND-function of the two data inputs (DSA and
DSB) that existed one set-up time prior to the rising clock edge.
A LOW on the master reset input (MR) overrides all other inputs and clears the register
asynchronously, forcing all outputs LOW.
2. Features
s Wide operating voltage: 1.0 V to 5.5 V
s Optimized for low-voltage applications: 1.0 V to 3.6 V
s Accepts TTL input levels between V_CC = 2.7 V and V_CC = 3.6 V
s Typical V_OLP (output ground bounce): < 0.8 V at V_CC = 3.3 V and T_amb = 25 °C
s Typical V_OHV (output V_OH undershoot): > 2 V at V_CC = 3.3 V and T_amb = 25 °C
s Gated serial data inputs
s Asynchronous master reset
s ESD protection:
x HBM EIA/JESD22-A114-B exceeds 2000 V
x MM EIA/JESD22-A115-A exceeds 200 V.
s Specified from −40 °C to +80 °C and from −40 °C to +125 °C.
3. Quick reference data
Table 1: Quick reference data
GND = 0 V; T_amb = 25 °C; t_r = t_f ≤ 2.5 ns.
Symbol Parameter
Conditions
t_PHL,
t_PLH
propagation delay
CP to Qn
V_CC = 3.3 V; C_L = 15 pF
MR to Qn
Min Typ Max Unit
-
12 -
ns
-
12 -
ns