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74HC_HCT257_15 Datasheet, PDF (1/18 Pages) NXP Semiconductors – Quad 2-input multiplexer; 3-state | |||
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74HC257; 74HCT257
Quad 2-input multiplexer; 3-state
Rev. 6 â 26 January 2015
Product data sheet
1. General description
The 74HC257; 74HCT257 are high-speed Si-gate CMOS devices and are pin compatible
with Low-power Schottky TTL (LSTTL).
The 74HC257 and 74HCT257 have four identical 2-input multiplexers with 3-state outputs,
which select 4 bits of data from two sources and are controlled by a common data select
input (S).
The data inputs from source 0 (1I0 to 4I0) are selected when input S is LOW and the data
inputs from source 1 (1I1 to 4I1) are selected when S is HIGH. Data appears at the
outputs (1Y to 4Y) in true (non-inverting) form from the selected inputs.
The 74HC257 and 74HCT257 are the logic implementation of a 4-pole, 2-position switch,
where the position of the switch is determined by the logic levels applied to S. The outputs
are forced to a high-impedance OFF-state when OE is HIGH.
The logic equations for the outputs are:
1Y = OE ï· ï¨1I1 ï· S ï· 1I0 ï· Sï©
2Y = OE ï· ï¨2I1 ï· S ï· 2I0 ï· Sï©
3Y = OE ï· ï¨3I1 ï· S ï· 3I0 ï· Sï©
4Y = OE ï· ï¨4I1 ï· S ï· 4I0 ï· Sï©
Except for their non-inverting (true) outputs the 74HC257; 74HCT257 are identical to the
74HC258.
2. Features and benefits
ï® Non-inverting data path
ï® 3-state outputs interface directly with system bus
ï® Complies with JEDEC standard no. 7A
ï® ESD protection:
ïµ HBM JESD22-A114F exceeds 2000 V
ïµ MM JESD22-A115-A exceeds 200 V
ï® Multiple package options
ï® Specified from ï40 ï°C to +85 ï°C and from ï40 ï°C to +125 ï°C
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