74F323 Datasheet, PDF (1/7 Pages) NXP Semiconductors – 8-bit universal shift/storage register with synchronous reset and common I/O pins 3-State

Philips Semiconductors
8-bit universal shift/storage register with synchronous
reset and common I/O pins (3-State)
Product specification
74F323
FEATURES
• Common parallel I/O for reduced pin count
• Additional serial inputs and outputs for expansion
• Four operating modes: Shift left, shift right, load, and store
• 3-State outputs for bus-oriented applications
DESCRIPTION
The 74F323 is an 8-bit universal shift/storage register with 3-State
outputs. Its function is similar to the 74F299 with the exception of
synchronous Reset. Parallel load inputs and flip-flop outputs are
multiplexed to minimize pin counts. Separate serial inputs and
outputs are provided for flip-flops Q0 and Q7 to allow easy serial
cascading. Four modes of operation are possible: Hold (store), shift
left, shift right, and parallel load.
The 74F323 contains eight edge-triggered D-type flip-flops and the
interstage logic necessary to perform synchronous reset, shift left,
shift right, parallel load, and hold operations. The type of operation is
determined by S0 and S1, as shown in the Function Table. All
flip-flop outputs are brought out through 3-State buffers to separate
I/O pins that also serve as data inputs in the parallel load mode.
Q0 and Q7 are also brought out on other pins for expansion in serial
shifting of longer words.
A Low signal on SR overrides the Select and inputs and allows the
flip-flops to be reset by the next rising edge of clock. All other state
changes are initiated by the rising edge of the clock. Inputs can
change when the clock is in either state provided only that the
recommended setup and hold times, relative to the rising edge of
clock are observed.
A High signal on either OE0 or OE1 disables the 3-State buffers and
puts the I/O pins in the high impedance state. In this condition the
shift, hold, load and reset operations can still occur. The 3-State
buffers are also disabled by High signals on both S0 and S1 in
preparation for a parallel load operation.
PIN CONFIGURATION
S0 1
OE0 2
OE1 3
I/O6 4
I/O4 5
I/O2 6
I/O0 7
Q0 8
SR 9
GND 10
20 V_CC
19 S1
18 DS7
17 Q7
16 I/O7
15 I/O5
14 I/O3
13 I/O1
12 CP
11 DS0
SF00888
TYPE
74F323
TYPICAL f_MAX
115MHz
TYPICAL
SUPPLY CURRENT
(TOTAL)
55mA
ORDERING INFORMATION
DESCRIPTION
20-pin plastic DIP
ORDER CODE
COMMERCIAL RANGE
V_CC = 5V ±10%, T_amb = 0°C to +70°C
N74F323N
20-pin plastic SOL
N74F323D
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
DESCRIPTION
74F(U.L.)
HIGH/LOW
DS0
Serial data input for right shift
1.0/1.0
DS7
Serial data input for left shift
1.0/1.0
S0, S1
Mode select inputs
1.0/2.0
CP
Clock pulse input (Active rising edge)
1.0/1.0
SR
Synchronous Reset input (Active Low)
1.0/1.0
OE0, OE1 Output Enable input (Active Low)
1.0/1.0
Q0, Q7
Serial outputs
50/33
Multiplexed parallel data inputs or
I/On
3-State parallel outputs
NOTE: One (1.0) FAST Unit Load (U.L.) is defined as: 20µA in the High State and 0.6mA in the Low state.
3.5/1.0
150/40
LOAD VALUE
HIGH/LOW
20µA/0.6mA
20µA/0.6mA
20µA/1.2mA
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
20µA/20mA
70µA/0.6mA
3.0mA/24mA
1990 Mar 01
1
853-0367 98987