74F224 Datasheet, PDF (1/1 Pages) NXP Semiconductors – 16 × 4 Synchronous FIFO 3-State

Philips Semiconductors FAST Products
16 × 4 Synchronous FIFO (3-State)
Preliminary specification
74F224
FEATURES
• Independent synchronous inputs and
outputs
• Organized as 16 words of 4 bits
• DC to 50MHz data rate
• 3-State outputs
• Cascadable in word–width and depth
direction
DESCRIPTION
This 64-bit active element First-In-First-Out
(FIFO) is a monolithic Schottky-clamped
transistor-transistor logic (STLL) array
organized as 16 words of 4-bits each. A
memory system using the 74F224 can be
easily expanded in multiples of 15m+1 words
or of 4n bits, or both (where n is the number
of packages in the horizontal array).
However, an external gating is required (see
Figure 1). For longer words using 74F224,
the IR signals of the first-rank packages and
OR signals of the last-rank packages must be
ANDed for proper synchronization.The
3-State outputs controlled by a single input
(OE) make bus connection and multiplexing
easy.
TYPE
74F224
TYPICAL
f_max
50MHz
TYPICAL
SUPPLY
CURRENT
(TOTAL)
90mA
ORDERING INFORMATION
DESCRIPTION
16-pin plastic Dual In-line Package
16-pin plastic Small Outline Large
ORDER CODE
COMMERCIAL RANGE
V_CC = 5V ±10%, T_amb = 0°C to +70°C
N74F224N
N74F224D
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS
DESCRIPTION
LDCP
Load clock input
D0 – D3
Data inputs
OE
Output enable input (active high)
UNCP
Unload clock input
MR
Master reset input (active low)
IR
Input ready output
Q0 – Q3
Data outputs
OR
Output ready output
NOTE TO INPUT AND OUTPUT LOADING AND FAN OUT TABLE
1. One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state.
74F (U.L.)
HIGH/LOW
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
50/33
50/33
50/33
DRAWING NUMBER
0406C
0171B
LOAD VALUE
HIGH/LOW
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
1.0mA/20mA
1.0mA/20mA
1.0mA/20mA
PIN CONFIGURATION
OE ¹
IR 2
LDCP 3
D0 4
D1 5
D2 6
D3 7
GND 8
16 _VCC
15 _UNCP
14 _OR
13 Q0
12 Q1
11 Q2
10 _Q3
9 MR
September 7, 1990
LOGIC SYMBOL
4 5 67
D0 D1 D2 D3
1
OE
13
UNCP
3
LDCP
9
MR
Q0 Q1 Q2 Q3 IR OR
V_CC = Pin 16
GND = Pin 8
13 12 11 10 2 14
1
IED/IEEE SYMBOL
FIFO 16 X 4
1
EN5
CTR
9
CT=0
CT<0 &
+/C1
2
2
3
Z2
3
14
CT>0 ^&
– ^{CT=0 &}
15
Z3
2
V4
4
1D
5
4,5
13
12
6
13
7
10