74F199 Datasheet, PDF (1/8 Pages) NXP Semiconductors – 8-bit parallel-access shift register

Philips Semiconductors FAST Products
8-bit parallel-access shift register
Product specification
74F199
FEATURES
• Buffered clock and control inputs
• Shift right and parallel load capability
• Fully synchronous data transfers
• J-K(D) inputs to first stage
• Clock enable for hold (do nothing) mode
• Asynchronous Master Reset
DESCRIPTION
The 74F199 is an 8-bit Parallel Access Shift Register and its
functional characteristics are indicated in the Logic Diagram and
Function Table. The device is useful in a variety of shifting, counting
and storage applications. It performs serial, parallel, serial-to-parallel,
or parallel–to-serial data transfers at very high speeds.
The 74F199 operates in two primary modes: shift right (Q0→Q1)
and parallel load, which are controlled by the state of the Parallel
Enable (PE) input. Serial data enters the first flip-flop (Q0) via the J
and K inputs when the PE input is High, and is shifted one bit in the
direction Q0→Q1→Q2 following each Low-to-High clock transition.
The J and K inputs provide the flexibility of the J-K type input for
special applications, and by tying the two together the simple D-type
input is made for general applications.
The device appears as eight common clocked D flip-flops when the
PE input is Low. After the Low-to-High clock transition, data on the
parallel inputs (D0–D7) is transferred to the respective Q0–Q7
outputs.
All parallel and serial data transfers are synchronous, occurring after
each Low-to-High clock transition. The 74F199 utilizes
edge-triggered, therefore there is no restriction on the activity of the
J, K, Dn, and PE inputs for logic operation, other than the setup and
hold time requirements.
A Low on the Master Reset (MR) input overrides all other inputs and
clears the register asynchronously forcing all bit positions to a Low
state.
PIN CONFIGURATION
K1
J2
D0 ³
Q0 ⁴
D1 ⁵
Q1 ⁶
D2 ⁷
Q2 ⁸
D3 ⁹
Q3 ¹⁰
CE ¹¹
GND 12
24 V_CC
23 _PE
22 _D7
21 _Q7
20 _D6
19 _Q6
18 _D5
17 _Q5
16 _D4
15 _Q4
14 _MR
13 _CP
SF00152
TYPE
74F199
TYPICAL f_MAX
95MHz
TYPICAL
SUPPLY CURRENT
(TOTAL)
70mA
ORDERING INFORMATION
DESCRIPTION
24-pin plastic slim DIP
(300mil)
COMMERCIAL RANGE
V_CC = 5V ±10%, T_amb = 0°C to +70°C
N74F199N
24-pin plastic SOL
N74F199D
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
DESCRIPTION
74F (U.L.) HIGH/LOW
D0–D7
Parallel data inputs
1.0/1.0
J, K
J and K inputs
1.0/1.0
PE
Parallel Enable input
1.0/1.0
CE
Clock Enable input
1.0/1.0
DP
Clock Pulse inputs (Active rising edge)
1.0/1.0
MR
Master Reset input (Active Low)
1.0/1.0
Q0–Q7
Data outputs
50/33
NOTE: One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.
LOAD VALUE HIGH/LOW
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
1.0mA/20mA
June 15, 1988
1
853–0082 93568