74F114 Datasheet, PDF (1/6 Pages) Fairchild Semiconductor – Dual JK Negative Edge-Triggered Flip-Flop with Common Clocks and Clears

Philips Semiconductors
Dual J-K negative edge-triggered flip-flop
with common clock and reset
Product specification
74F114
DESCRIPTION
The 74F114, Dual Negative edge-triggered JK-Type Flip-Flop with
common clock and reset inputs, features individual J, K, Clock (CP),
Set (SD) and Reset (RD) inputs, true and complementary outputs.
The SD and RD inputs, when Low, set or reset the outputs as shown
in the Function Table regardless of the level at the other inputs.
A High level on the clock (CP) input enables the J and K inputs and
data will be accepted. The logic levels and data will be accepted.
The logic levels at the J and K inputs may be allowed to change
while the CP is High and flip-flop will perform according to the
Function Table as long as minimum setup and hold times are
observed. Output changes are initiated by the High-to-Low transition
of the CP.
TYPE
74F114
TYPICAL f_MAX
100MHz
TYPICAL
SUPPLY CURRENT
(TOTAL)
15mA
PIN CONFIGURATION
RD 1
K0 2
J0 3
SD0 4
Q0 5
Q0 6
GND 7
14 V_CC
13 CP
12 K1
11 J1
10 SD1
9 Q1
8 Q1
SF00110
ORDERING INFORMATION
DESCRIPTION
COMMERCIAL RANGE
V_CC = 5V ±10%,
T_amb = 0°C to +70°C
14-pin plastic DIP
N74F114N
14-pin plastic SO
N74F114D
PKG. DWG. #
SOT27-1
SOT108-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
DESCRIPTION
74F (U.L.) HIGH/LOW
J0, J1
J inputs
1.0/1.0
K0, K1
K inputs
1.0/1.0
SD0, SD1
Set inputs (active Low)
1.0/5.0
RD
Reset input (active Low)
1.0/10.0
CP
Clock Pulse input (active falling edge)
1.0/8.0
Q0, Q0; Q1, Q1
Data outputs
50/33
NOTE: One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.
LOGIC SYMBOL
IEC/IEEE SYMBOL
LOAD VALUE HIGH/LOW
20µA/0.6mA
20µA/0.6mA
20µA/3.0mA
20µA/6.0mA
20µA/4.8mA
1.0mA/20mA
13
4
1
10
V_CC = Pin 14
GND = Pin 7
3 11 2 12
J0 J1 K0 K1
CP
SD0
RD0
SD1
Q0 Q0 Q1 Q1
56 98
SF00111
1
R
13
C1
4
S
3
1K
2
1J
10
11
12
5
6
9
8
SF00112
1996 Mar 14
1
853–0340 16572