74AXP1G04_15 Datasheet, PDF (1/17 Pages) NXP Semiconductors – Low-power inverter

74AXP1G04
Low-power inverter
Rev. 1 — 25 August 2014
Product data sheet
1. General description
The 74AXP1G04 is a single inverting buffer.
Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall
times.
This device ensures very low static and dynamic power consumption across the entire
V_CC range from 0.7 V to 2.75 V. It is fully specified for partial power down applications
using I_OFF. The I_OFF circuitry disables the output, preventing the potentially damaging
backflow current through the device when it is powered down.
2. Features and benefits
 Wide supply voltage range from 0.7 V to 2.75 V
 Low input capacitance; C_I = 0.5 pF (typical)
 Low output capacitance; C_O = 1.0 pF (typical)
 Low dynamic power consumption; C_PD = 2.3 pF at V_CC = 1.2 V (typical)
 Low static power consumption; I_CC = 0.6 A (85 C maximum)
 High noise immunity
 Complies with JEDEC standard:
 JESD8-12A.01 (1.1 V to 1.3 V)
 JESD8-11A.01 (1.4 V to 1.6 V)
 JESD8-7A (1.65 V to 1.95 V)
 JESD8-5A.01 (2.3 V to 2.7 V)
 ESD protection:
 HBM ANSI/ESDA/JEDEC JS-001 Class 2 exceeds 2 kV
 CDM JESD22-C101E exceeds 1000 V
 Latch-up performance exceeds 100 mA per JESD 78 Class II
 Inputs accept voltages up to 2.75 V
 Low noise overshoot and undershoot < 10 % of V_CC
 I_OFF circuitry provides partial Power-down mode operation
 Multiple package options
 Specified from 40 C to +85 C