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74AUP2G132_15 Datasheet, PDF (1/23 Pages) NXP Semiconductors – Low-power dual 2-input NAND Schmitt trigger | |||
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74AUP2G132
Low-power dual 2-input NAND Schmitt trigger
Rev. 7 â 8 February 2013
Product data sheet
1. General description
The 74AUP2G132 provides the dual 2-input NAND Schmitt trigger function which accepts
standard input signals. They can transform slowly changing input signals into sharply
defined, jitter-free output signals.
This device ensures a very low static and dynamic power consumption across the entire
VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial power-down applications using IOFF. The IOFF
circuitry disables the output, preventing a damaging backflow current through the device
when it is powered down.
The inputs switch at different points for positive and negative-going signals. The difference
between the positive voltage VT+ and the negative voltage VTï is defined as the input
hysteresis voltage VH.
2. Features and benefits
ï® Wide supply voltage range from 0.8 V to 3.6 V
ï® High noise immunity
ï® ESD protection:
ïµ HBM JESD22-A114F Class 3A exceeds 5000 V
ïµ MM JESD22-A115-A exceeds 200 V
ïµ CDM JESD22-C101E exceeds 1000 V
ï® Low static power consumption; ICC = 0.9 ïA (maximum)
ï® Latch-up performance exceeds 100 mA per JESD 78 Class II
ï® Inputs accept voltages up to 3.6 V
ï® Low noise overshoot and undershoot < 10 % of VCC
ï® IOFF circuitry provides partial Power-down mode operation
ï® Multiple package options
ï® Specified from ï40 ï°C to +85 ï°C and ï40 ï°C to +125 ï°C
3. Applications
ï® Wave and pulse shaper
ï® Astable multivibrator
ï® Monostable multivibrator
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