74AUP1T45_15 Datasheet, PDF(1/36 Page) NXP Semiconductors – Low-power dual supply translating transceiver; 3-state

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74AUP1T45_15 Datasheet, PDF (1/36 Pages) NXP Semiconductors – Low-power dual supply translating transceiver; 3-state

74AUP1T45

Low-power dual supply translating transceiver; 3-state

Rev. 5 â 9 August 2012

Product data sheet

1. General description

The 74AUP1T45 is a single bit transceiver featuring two data input-outputs (A and B), a

direction control input (DIR) and dual supply pins (VCC(A) and VCC(B)) which enable

bidirectional level translation. Both VCC(A) and VCC(B) can be supplied at any voltage

between 1.1 V and 3.6 V making the device suitable for interfacing between any of the low

voltage nodes (1.2 V, 1.5 V, 1.8 V, 2.5 V and 3.3 V). Pins A and DIR are referenced to

VCC(A) and pin B is referenced to VCC(B). A HIGH on DIR allows transmission from A to B

and a LOW on DIR allows transmission from B to A.

Schmitt trigger action on all inputs makes the circuit tolerant of slower input rise and fall

times across the entire VCC(A) and VCC(B) ranges. The device ensures low static and

dynamic power consumption and is fully specified for partial power-down applications

using IOFF. The IOFF circuitry disables the output, preventing any damaging backflow

current through the device when it is powered down. In suspend mode when either VCC(A)

or VCC(B) are at GND, both A and B are in the high-impedance OFF-state.

2. Features and benefits

ï® Wide supply voltage range:

ïµ VCC(A): 1.1 V to 3.6 V

ïµ VCC(B): 1.1 V to 3.6 V

ï® High noise immunity

ï® Complies with JEDEC standards:

ïµ JESD8-7 (1.2 V to 1.95 V)

ïµ JESD8-5 (1.8 V to 2.7 V)

ïµ JESD8-B (2.7 V to 3.6 V)

ï® ESD protection:

ïµ HBM JESD22-A114F Class 3A exceeds 5000 V

ïµ MM JESD22-A115-A exceeds 200 V

ïµ CDM JESD22-C101E exceeds 1000 V

ï® Low static power consumption; ICC = 0.9 ïA (maximum)

ï® Suspend mode

ï® Latch-up performance exceeds 100 mA per JESD 78 Class II

ï® Inputs accept voltages up to 3.6 V

ï® Low noise overshoot and undershoot < 10 % of VCC

ï® IOFF circuitry provides partial power-down mode operation

ï® Multiple package options

ï® Specified from ï40 ï°C to +85 ï°C and ï40 ï°C to +125 ï°C

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