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74AUP1G97 Datasheet, PDF (1/19 Pages) NXP Semiconductors – Low-power configurable multiple function gate | |||
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74AUP1G97
Low-power conï¬gurable multiple function gate
Rev. 01 â 7 November 2006
Product data sheet
1. General description
The 74AUP1G97 is a high-performance, low-power, low-voltage, Si-gate CMOS device,
superior to most advanced CMOS compatible TTL families.
This device ensures a very low static and dynamic power consumption across the entire
VCC range from 0.8 V to 3.6 V.
This device is fully speciï¬ed for partial power-down applications using IOFF.
The IOFF circuitry disables the output, preventing the damaging backï¬ow current through
the device when it is powered down.
The 74AUP1G97 provides conï¬gurable multiple functions. The output state is determined
by eight patterns of 3-bit input. The user can choose the logic functions MUX, AND, OR,
NAND, NOR, inverter and buffer. All inputs can be connected to VCC or GND.
Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall
times across the entire VCC range from 0.8 V to 3.6 V.
The inputs switch at different points for positive and negative-going signals. The difference
between the positive voltage VT+ and the negative voltage VTâ is deï¬ned as the input
hysteresis voltage VH.
2. Features
s Wide supply voltage range from 0.8 V to 3.6 V
s High noise immunity
s ESD protection:
x HBM JESD22-A114-D Class 3A exceeds 5000 V
x MM JESD22-A115-A exceeds 200 V
x CDM JESD22-C101-C exceeds 1000 V
s Low static power consumption; ICC = 0.9 µA (maximum)
s Latch-up performance exceeds 100 mA per JESD 78 Class II
s Inputs accept voltages up to 3.6 V
s Low noise overshoot and undershoot < 10 % of VCC
s IOFF circuitry provides partial Power-down mode operation
s Multiple package options
s Speciï¬ed from â40 °C to +85 °C and â40 °C to +125 °C
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