74AUP1G885 Datasheet, PDF (1/19 Pages) NXP Semiconductors – Low-power dual function gate

74AUP1G885
Low-power dual function gate
Rev. 01.00 — 26 January 2006
Preliminary data sheet
1. General description
The 74AUP1G885 is a high-performance, low-power, low-voltage, Si-gate CMOS device,
superior to most advanced CMOS compatible TTL families.
Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall
times across the entire V_CC range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire
V_CC range from 0.8 V to 3.6 V.
This device is fully specified for partial Power-down applications using I_OFF.
The I_OFF circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
The 74AUP1G885 provides two functions in one device.The output state of the outputs
(1Y, 2Y) is determined by the inputs (A, B and C). The output 1Y provides the boolean
funtion: 1Y = A × C. The output 2Y provides the boolean funtion: 2Y = A × B + A × C
2. Features
s Wide supply voltage range from 0.8 V to 3.6 V
s High noise immunity
s Complies with JEDEC standards:
x JESD8-12 (0.8 V to 1.3 V)
x JESD8-11 (0.9 V to 1.65 V)
x JESD8-7 (1.2 V to 1.95 V)
x JESD8-5 (1.8 V to 2.7 V)
x JESD8-B (2.7 V to 3.6 V)
s ESD protection:
x HBM JESD22-A114-C Class 3A exceeds 4000 V
x MM JESD22-A115-A exceeds 200 V
x CDM JESD22-C101-C exceeds 1000 V
s Low static power consumption; I_CC = 0.9 µA (maximum)
s Latch-up performance exceeds 100 mA per JESD 78 Class II
s Inputs accept voltages up to 3.6 V
s Low noise overshoot and undershoot < 10 % of V_CC
s I_OFF circuitry provides partial Power-down mode operation
s Multiple package options
s Specified from −40 °C to +85 °C and −40 °C to +125 °C