74AUP1G74 Datasheet, PDF (1/23 Pages) NXP Semiconductors – Low-power D-type flip-flop with set and reset; positive-edge trigger

74AUP1G74
Low-power D-type flip-flop with set and reset; positive-edge
trigger
Rev. 01 — 25 August 2006
Product data sheet
1. General description
The 74AUP1G74 is a high-performance, low-power, low-voltage, Si-gate CMOS device,
superior to most advanced CMOS compatible TTL families.
Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall
times across the entire V_CC range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire
V_CC range from 0.8 V to 3.6 V.
This device is fully specified for partial Power-down applications using I_OFF.
The I_OFF circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
The 74AUP1G74 provides the single positive-edge triggered D-type flip-flop with
individual data (D) input, clock (CP) input, set (SD) and reset (RD) inputs and
complementary Q and Q outputs. The set and reset are asynchronous active LOW inputs
and operate independently of the clock input. Information on the data input is transferred
to the Q output on the LOW-to-HIGH transition of the clock pulse. The D input must be
stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation.
2. Features
s Wide supply voltage range from 0.8 V to 3.6 V
s High noise immunity
s Complies with JEDEC standards:
x JESD8-12 (0.8 V to 1.3 V)
x JESD8-11 (0.9 V to 1.65 V)
x JESD8-7 (1.2 V to 1.95 V)
x JESD8-5 (1.8 V to 2.7 V)
x JESD8-B (2.7 V to 3.6 V)
s ESD protection:
x HBM JESD22-A114-D Class 3A exceeds 5000 V
x MM JESD22-A115-A exceeds 200 V
x CDM JESD22-C101-C exceeds 1000 V
s Low static power consumption; I_CC = 0.9 µA (maximum)
s Latch-up performance exceeds 100 mA per JESD 78 Class II
s Inputs accept voltages up to 3.6 V
s Low noise overshoot and undershoot < 10 % of V_CC