74AUP1G57 Datasheet, PDF (1/22 Pages) NXP Semiconductors – Low-power configurable multiple function gate

74AUP1G57
Low-power configurable multiple function gate
Rev. 01. — 16 January 2006
Preliminary data sheet
1. General description
The 74AUP1G57 is a high-performance, low-power, low-voltage, Si-gate CMOS device,
superior to most advanced CMOS compatible TTL families.
This device ensures a very low static and dynamic power consumption across the entire
V_CC range from 0.8 V to 3.6 V.
This device is fully specified for partial Power-down applications using I_OFF.
The I_OFF circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
The 74AUP1G57 provides configurable multiple functions. The output state is determined
by eight patterns of 3-bit input. The user can choose the logic functions AND, OR, NAND,
NOR, XNOR, inverter and buffer. All inputs can be connected to V_CC or GND.
Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall
times across the entire V_CC range from 0.8 V to 3.6 V.
The inputs switch at different points for positive and negative-going signals. The difference
between the positive voltage V_T+ and the negative voltage V_T− is defined as the input
hysteresis voltage V_H.
2. Features
s Wide supply voltage range from 0.8 V to 3.6 V
s High noise immunity
s ESD protection:
x HBM JESD22-A114-C Class 3A. Exceeds 5000 V
x MM JESD22-A115-A exceeds 200 V
x CDM JESD22-C101-C exceeds 1000 V
s Low static power consumption; I_CC = 0.9 µA (maximum)
s Latch-up performance exceeds 100 mA per JESD 78 Class II
s Inputs accept voltages up to 3.6 V
s Low noise overshoot and undershoot < 10 % of V_CC
s I_OFF circuitry provides partial Power-down mode operation
s Multiple package options
s Specified from −40 °C to +85 °C and −40 °C to +125 °C