74AUP1G132_15 Datasheet, PDF (1/22 Pages) NXP Semiconductors – Low-power 2-input NAND Schmitt trigger

74AUP1G132
Low-power 2-input NAND Schmitt trigger
Rev. 5 — 29 June 2012
Product data sheet
1. General description
The 74AUP1G132 provides the single 2-input NAND Schmitt trigger function which accept
standard input signals. They are capable of transforming slowly changing input signals
into sharply defined, jitter-free output signals.
This device ensures a very low static and dynamic power consumption across the entire
V_CC range from 0.8 V to 3.6 V.
This device is fully specified for partial Power-down applications using I_OFF.
The I_OFF circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
The inputs switch at different points for positive and negative-going signals. The difference
between the positive voltage V_T+ and the negative voltage V_T is defined as the input
hysteresis voltage V_H.
2. Features and benefits
 Wide supply voltage range from 0.8 V to 3.6 V
 High noise immunity
 ESD protection:
 HBM JESD22-A114F Class 3A exceeds 5000 V
 MM JESD22-A115-A exceeds 200 V
 CDM JESD22-C101E exceeds 1000 V
 Low static power consumption; I_CC = 0.9 A (maximum)
 Latch-up performance exceeds 100 mA per JESD 78 Class II
 Inputs accept voltages up to 3.6 V
 Low noise overshoot and undershoot < 10 % of V_CC
 I_OFF circuitry provides partial Power-down mode operation
 Multiple package options
 Specified from 40 C to +85 C and 40 C to +125 C
3. Applications
 Wave and pulse shaper
 Astable multivibrator
 Monostable multivibrator.