74ALVT16827_15 Datasheet, PDF (1/16 Pages) NXP Semiconductors – 20-bit buffer/line driver; non-inverting; 3-state

74ALVT16827
20-bit buffer/line driver; non-inverting; 3-state
Rev. 03 — 2 June 2005
Product data sheet
1. General description
The 74ALVT16827 high-performance BiCMOS device combines low static and dynamic
power dissipation with high speed and high output drive. It is designed for V_CC operation
at 2.5 V or 3.3 V with I/O compatibility to 5 V.
The 74ALVT16827 20-bit buffers provide high performance bus interface buffering for wide
data/address paths or buses carrying parity. They have NOR Output Enables (nOE1 and
nOE2) for maximum control flexibility.
2. Features
s Multiple V_CC and GND pins minimize switching noise
s 5 V I/O compatible
s Live insertion and extraction permitted
s 3-state output buffers
s Power-up 3-state
s Output capability: +64 mA and −32 mA
s Latch-up protection:
x JESD 78 exceeds 500 mA
s ElectroStatic Discharge (ESD) protection:
x MIL STD 883 Method 3015: exceeds 2000 V
x Machine model: exceeds 200 V
s Bus hold data inputs eliminate need for external pull-up resistors to hold unused inputs
3. Quick reference data
Table 1: Quick reference data
GND = 0 V; T_amb = 25 °C.
Symbol Parameter
Conditions
t_PLH
propagation delay nAx C_L = 50 pF; V_CC = 2.5 V
to nYx
C_L = 50 pF; V_CC = 3.3 V
t_PHL
propagation delay nAx C_L = 50 pF; V_CC = 2.5 V
to nYx
C_L = 50 pF; V_CC = 3.3 V
C_I
input capacitance on V_I = 0 V or V_CC
DIR, OE
Min Typ Max Unit
1.0
2.0
2.9
ns
0.7
1.5
2.2
ns
1.0
2.0
3.0
ns
0.8
1.6
2.3
ns
-
3
-
pF