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74ALVT16601_05 Datasheet, PDF (1/20 Pages) NXP Semiconductors – 18-bit universal bus transceiver; 3-state | |||
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74ALVT16601
18-bit universal bus transceiver; 3-state
Rev. 03 â 5 July 2005
Product data sheet
1. General description
The 74ALVT16601 is a high-performance Bipolar Complementary Metal Oxide
Semiconductor (BiCMOS) product designed for VCC operation at 2.5 V and 3.3 V with I/O
compatibility up to 5 V. This device is an 18-bit universal transceiver featuring
non-inverting 3-state bus compatible outputs in both send and receive directions. Data
ï¬ow in each direction is controlled by output enable (OEAB and OEBA), latch enable
(LEAB and LEBA), and clock (CPAB and CPBA) inputs. For A-to-B data ï¬ow, the device
operates in the transparent mode when LEAB is HIGH. When LEAB is LOW, the A-bus
data is latched if CPAB is held at a HIGH or LOW level. If LEAB is LOW, the A-bus data is
stored in the latch/ï¬ip-ï¬op on the LOW-to-HIGH transition of CPAB. When OEAB is LOW,
the outputs are active. When OEAB is HIGH, the outputs are in the high-impedance state.
The clocks can be controlled with the clock enable inputs (CEAB and CEBA).
Data ï¬ow for B-to-A is similar to that of A-to-B but uses OEBA, LEBA and CPBA.
Active bus hold circuitry is provided to hold unused or ï¬oating data inputs at a valid logic
level.
2. Features
s 18-bit bidirectional bus interface
s 5 V I/O compatible
s 3-state buffers
s Output capability: +64 mA and â32 mA
s TTL input and output switching levels
s Input and output interface capability to systems at 5 V supply
s Bus hold data inputs eliminate the need for external pull-up resistors to hold unused
inputs
s Live insertion and extraction permitted
s Power-up reset
s Power-up 3-state
s No bus current loading when output is tied to 5 V bus
s Positive-edge triggered clock inputs
s Latch-up protection:
x JESD78: exceeds 500 mA
s ESD protection:
x MIL STD 883, method 3015: exceeds 2000 V
x Machine model: exceeds 200 V
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