74ALVCH16952_15 Datasheet, PDF (1/17 Pages) NXP Semiconductors – 16-bit registered transceiver; 3-state

74ALVCH16952
16-bit registered transceiver; 3-state
Rev. 02 — 27 April 2006
Product data sheet
1. General description
The 74ALVCH16952 consists of two sections, each containing a dual octal non-inverting
registered transceiver. Two 8-bit back to back registers store data flowing in both
directions between two bidirectional buses. Data applied to the inputs is entered and
stored on the rising edge of the clock (nCPAB and nCPBA) provided that the clock enable
(nCEAB and nCEBA) is LOW. The data is then present at the output buffers, but is only
accessible when the output enable input (nOEAB and nOEBA) is LOW. Data flow from A
inputs to B outputs is the same as for B inputs to A outputs.
2. Features
I CMOS low-power consumption
I Multibyte flow-through pinout architecture
I Low inductance, multiple center power and ground pins for minimum noise and ground
bounce
I Direct interface with TTL levels
I Output drive capability 50 Ω transmission lines at 85 °C
I Complies with JEDEC standard JESD8-B
3. Quick reference data
Table 1. Quick reference data
GND = 0 V; T_amb = 25 °C; t_r = t_f = 2.5 ns.
Symbol Parameter
Conditions
Min Typ Max Unit
t_PHL,
t_PLH
f_max
propagation delay
nCPBA to nAn; nCPAB to nBn V_CC = 3.3 V; C_L = 50 pF
V_CC = 2.5 V; C_L = 30 pF
maximum input clock
frequency
V_CC = 3.3 V
- 3.2 - ns
- 3.2 - ns
- 350 - MHz
C_i
input capacitance
- 3.0 - pF
C_PD
power dissipation capacitance per buffer; V_I = GND to V_CC ^[1] -
30 -
pF
[1] C_PD is used to determine the dynamic power dissipation (P_D in µW).
P_D = C_PD × V_CC2 × f_i × N + Σ(C_L × V_CC2 × f_o) where:
f_i = input frequency in MHz;
f_o = output frequency in MHz;
C_L = output load capacitance in pF;
V_CC = supply voltage in Volts;
N = number of inputs switching;
Σ(C_L × V_CC2 × f_o) = sum of outputs.